Generalized mergeability in space compression using nonexhaustive test patterns for built-in self-testing of VLSI circuits: Mathematical analysis and simulation results.

Barakat, T.F.

doi:10.20381/ruor-13661

1998

DOI: 10.20381/ruor-13661

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Generalized mergeability in space compression using nonexhaustive test patterns for built-in self-testing of VLSI circuits: Mathematical analysis and simulation results.

T.F. Barakat¹

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Generalized mergeability in space compression using nonexhaustive test patterns for built-in self-testing of VLSI circuits: Mathematical analysis and simulation results.

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