Generating Reduced Order Models for High Speed VLSI Interconnects using Balancing-Free Square Root Method

Abstract

This paper presents a model order reduction tech-Such reduced-order models can be used to predict the timenique based on balancing-free square root (BSR) method for domain or frequency-domain response of the linear network.high speed coupled integrated circuit interconnects. The salient A multipoint moment-matching or complex frequency hopping features of this technique are the less CPU time resulting from the passivity of the reduced transfer function, and the (CFH) technique extracts accurate dominant poles of a linear availability of provable weighted error bounds for the reduced-sub-network up to any predefined maximum frequency. This order system. This paper shows that the balancing-free square method generates a single transfer function for a large linear root method produces reduced systems that accurately follow sub-network and provides for a CPU/accuracy tradeoff. Model the time-and frequency-domain responses of the original order reduction can also be obtained using projecting the system. All the experiments have been carried out using Cadence Design Simulator which indicate that the proposed BSR achieves origial system described by nonlinear differential equations more accuracy with less CPU time than the other model order into krylov subspace of lower dimension. This reduced model reduction techniques existing in literature.can be simulated using conventional numerical techniques. Simulation of interconnects can also be performed treating