Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks

Engel, Andreas; Koch, Andreas

doi:10.1007/978-3-319-05960-0_15

Cited by 6 publications

(8 citation statements)

References 12 publications

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“…It is shown in equation (12) that energy efficiency of data compression algorithms is not only related to the compression ratio R c , but is also affected by algorithms and hardware. So h E can be obtained by testing or calculating hardware coefficient k, software coefficient s, and compression ratio R c .…”

Section: Evaluation Schemementioning

confidence: 99%

“…It can be also known that h E is less than R c , and increasing R c or decreasing the ratio of s to k can enlarge h E . Furthermore, equation (12) indicates the methods to improve the energy efficiency of algorithms.…”

Section: Evaluation Schemementioning

confidence: 99%

“…The larger the absolute value of h E , the more the energy consumption. As shown in equation (12), the necessary condition of energy saving is R c . 0.…”

Section: Evaluation Schemementioning

confidence: 99%

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A new scheme for evaluating energy efficiency of data compression in wireless sensor networks

Liu

Chen

et al. 2018

International Journal of Distributed Sensor Networks

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Data communication incurs the highest energy cost in wireless sensor networks, and restricts the application of wireless sensor networks. Data compression is a promising technique that can reduce the amount of data exchanged between nodes and results in energy saving. However, there is a lack of effective methods to evaluate the efficiency of data compression algorithms and to increase nodes' energy efficiency. The energy saving of nodes is related to both hardware and software, this article proposes a new scheme for evaluating energy efficiency of data compression in wireless sensor networks according to the node's hardware and software. The relationship between the energy efficiency and the hardware and software factors is expressed by a formula. In this formula, energy efficiency can be improved by increasing the compression ratio and decreasing the ratio of s/k, in which k represents the node's hardware factor related to energy consumption of processor, wireless module, and so on and s represents the software factor that reflects the energy consumption of the algorithm. Based on the scheme, a mechanism is proposed to improve the node's energy efficiency by selecting effective algorithms in accordance with the node's radio frequency power. The feasibility of the scheme is demonstrated with lossless data compression algorithms on the MSP430F2618 processor.

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Section: Evaluation Schemementioning

confidence: 99%

Section: Evaluation Schemementioning

confidence: 99%

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A new scheme for evaluating energy efficiency of data compression in wireless sensor networks

Liu

Chen

et al. 2018

International Journal of Distributed Sensor Networks

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“…Furthermore, a HaLOEWEn hardware accelerator is detailed, whose energy efficiency is evaluated for two concrete examples in Section 7.1 and 7.2. The implementation and evaluation of the compression kernel have already been published in [Engel2014a].…”

Section: Lossless Data Compressionmentioning

confidence: 99%

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications

Engel

Koch

Siebel

2015

2015 IEEE 40th Local Computer Networks Conference Workshops (LCN Workshops)

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Die Veröffentlichung steht unter folgender Creative Commons Lizenz: Namensnennung -Keine kommerzielle Nutzung -Keine Bearbeitung 4.0 International https://creativecommons.org/licenses/by-nc-nd/4.0 Erklärung zur DissertationHiermit versichere ich, die vorliegende Dissertation ohne Hilfe Dritter nur mit den angegebenen Quellen und Hilfsmitteln angefertigt zu haben. Alle Stellen, die aus Quellen entnommen wurden, sind als solche kenntlich gemacht. Diese Arbeit hat in gleicher oder ähnlicher Form noch keiner Prüfungsbehörde vorgelegen. Darmstadt, den 22.11.2016 (Andreas Engel) AbstractWireless Sensor Networks (WSNs) combine embedded sensing and processing capabilities with a wireless communication infrastructure, thus supporting distributed monitoring applications. WSNs have been investigated for more than three decades, and recent social and industrial developments such as home automation, or the Internet of Things, have increased the commercial relevance of this key technology. The communication bandwidth of the sensor nodes is limited by the transportation media and the restricted energy budget of the nodes. To still keep up with the ever increasing sensor count and sampling rates, the basic data acquisition and collection capabilities of WSNs have been extended with decentralized smart feature extraction and data aggregation algorithms. Energy-efficient processing elements are thus required to meet the ever-growing compute demands of the WSN motes within the available energy budget.The Hardware-Accelerated Low Power Mote (HaLoMote) is proposed and evaluated in this thesis to address the requirements of compute-intensive WSN applications. It is a heterogeneous system architecture, that combines a Field Programmable Gate Array (FPGA) for hardware-accelerated data aggregation with an IEEE 802.15.4 based Radio Frequency System-on-Chip for the network management and the top-level control of the applications. To properly support Dynamic Power Management (DPM) on the HaLoMote, a Microsemi IGLOO FPGA with a non-volatile configuration storage was chosen for a prototype implementation, called Hardware-Accelerated Low Energy Wireless Embedded Sensor Node (HaLOEWEn). As for every multi-processor architecture, the inter-processor communication and coordination strongly influences the efficiency of the HaLoMote. Therefore, a generic communication framework is proposed in this thesis. It is tightly coupled with the DPM strategy of the HaLoMote, that supports fast transitions between active and idle modes. Low-power sleep periods can thus be scheduled within every sampling cycle, even for sampling rates of hundreds of hertz.In addition to the development of the heterogeneous system architecture, this thesis focuses on the energy consumption trade-off between wireless data transmission and insensor data aggregation. The HaLOEWEn is compared with typical software processors in terms of runtime and energy efficiency in the context of three monitoring applications. The building blocks of these applications comprise hardware-acce...

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“…An implementation of an adaptive differential pulse code modulation (ADPCM) taken from [17] was used as an application example. ADPCM is used for example in ITU audio codec G.726 for IP telephony [18] like in DECT for cordless phones.…”

Section: Adpcm As An Application Examplementioning

confidence: 99%

Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors

Hochberger

Jung

Engel

et al. 2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

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Abstract-The large expense of current chip fabrication can generally only be amortized for large manufacturing volumes. Thus, it is desirable to build adaptable chips that can be customized to the application needs after production. In this contribution we show that this adaptation is possible even without reconfigurable HW components. We propose synthilation, a new method for adapting the processor to the application requirements. It combines methods of hardware synthesis and software compilation to map high-level descriptions to hardware components of the processor. Our approach is applicable to varying degrees of reconfigurability, reaching from static microarchitectures just with writable control stores (variable microcode), to the exploitation of instruction level parallelism with multiple computational units. We consider both a practical real-world example as well as theoretical bounds on the speed-ups achievable by our method.

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Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks

Cited by 6 publications

References 12 publications

A new scheme for evaluating energy efficiency of data compression in wireless sensor networks

A new scheme for evaluating energy efficiency of data compression in wireless sensor networks

A heterogeneous system architecture for low-power wireless sensor nodes in compute-intensive distributed applications

Synthilation: JIT-compilation of microinstruction sequences in AMIDAR processors

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