Hardware Implementation and Comparison of New Defuzzification Techniques in Fuzzy Processors

Abstract

This paper deals with hardware implementation defuzzification method according to the nature of the aspects of the defuzzification block in fuzzy controllers and application [8] and also the trade-off between accuracy processors. Three new defuzzification methods are introduced (defuzzified output error) and computational power demand which are suitable for low cost hardware implementation. A (hardware complexity or software execution time). For complete set of common existing defuzzification methods are software implementation, there are some reports which reviewed to be compared with these new methods from determine the trade-off between output error and execution different hardware implementation aspects. Two different termin e deffication method executior hardware models with different structures are developed for time of different defuzzification methods [3], [4]. For each method. The first model realizes the full combinational or hardware implementation of a fuzzy controller however, fastest possible hardware implementation, and the second there are only some scattered works [5] and an integrated model demonstrates the full sequential or the smallest possible comprehensive study cannot be found.hardware implementation of each method. All models are This paper is organized as follows. In Section II, the synthesized on 0.18 micron CMOS technology cells to analyze paper terminology about naming of the existing and compare the area, delay and power consumption of defuzzification method is clarified and also a brief different realizations of defuzzification methods. Some areadescription of our three new methods is presented. Section power-delay-accuracy analysis diagrams are then introduced l l according to the synthesis results to guide the designers dII demonstrates the simulation results, and includes through choosing the defuzzification method and also the discussions about the defuzzified output accuracy analysis of implementation structure which best suites their application different defuzzification methods. The hardware models for from implementation cost, speed, power consumption and these defuzzification methods are then presented in Section output accuracy points of view.IV. Section V contains the area-delay-power synthesis results of the developed models. Section VI includes our conclusion