Hardware implementation and VLSI design of spectrum sensor for next‐generation LTE‐A cognitive‐radio wireless network

Murty, Mahesh S.; Shrestha, Rahul

doi:10.1049/iet-cds.2017.0292

Cited by 14 publications

(4 citation statements)

References 26 publications

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“…Murty and Shrestha developed range detecting in CR using the time space cyclostationary-highlight finder (TCD) [13]. This TCD is a reconfigurable, equipmentproductive VLSI plan.…”

Section: Related Workmentioning

confidence: 99%

Truncation Multiplier‐Based Cognitive Radio Spectrum Analyzer for Nanomedical Applications

Kumareshan¹,

Umashankar²,

Verma

et al. 2022

Journal of Nanomaterials

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The electromagnetic spectrum is one of nature’s meagre resources. The requirements of wireless communication cannot be satisfied by the new spectrum allocation plan. A policy of self-driven spectrum allocation results as a result. Cognitive radio (CR) engineering is a brilliant technique to maximise spectrum utilisation in rapidly changing environments by identifying unusable and underutilised bandwidth. One of the information strategies of intellectual radio is range detecting, which uses self-persuaded range allocation techniques to use open range to determine the existence of critical clients in the approved recurrence band. Energy location and cyclostationary highlight recognition are the two main factors that determine range detection. Energy recognition is a key method of range detection, but it becomes discouraging at low signal to noise ratios. With a cost of the highest degree of execution complexity, the critical cyclostationary highlight recognition based on cyclic range assessment may successfully identify weak signs from crucial clients. This project is aimed at implementing a useful range detecting mechanism in a field programmable door show with meticulous precision for CR. The adaptive absolute-self-coherent-restoral algorithm, specifically using the truncation multiplier, is a new spectrum sensing system. The proposed architecture, which makes use of a truncation multiplier, was created using the Xilinx approach. This study suggests an efficient spectrum sensing technique that makes use of the Adaptive Absolute Score (AAS) algorithm and SQRT-based Carry Select Adder (CSLA). The TM-CSLA design includes 228 LUT for the Spartan 6 device, which is fewer than the other architectures.

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“…Murty and Shrestha developed range detecting in CR using the time space cyclostationary-highlight finder (TCD) [13]. This TCD is a reconfigurable, equipmentproductive VLSI plan.…”

Section: Related Workmentioning

confidence: 99%

Truncation Multiplier‐Based Cognitive Radio Spectrum Analyzer for Nanomedical Applications

Kumareshan¹,

Umashankar²,

Verma

et al. 2022

Journal of Nanomaterials

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“…M.S. Murty and R. Shrestha [20] developed the spectrum sensing in CR by using the time domain cyclostationary-feature detector (TCD). This TCD is a reconfigurable and hardware-efficient VLSI architecture.…”

Section: Literature Surveymentioning

confidence: 99%

FPGA Implementation of Adaptive Absolute SCORE Algorithm for Cognitive Radio Spectrum Sensing with WTM and LFA

Kumar¹,

Bikshalu²

2021

IJIES

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Cognitive Radio (CR) is generally a wireless communication system that has the ability to improve the network’s system-capacity. Since, the white space or temporally unused spectrum are used to enhance the systemcapacity and the important operation involved in the cognition cycle is spectrum sensing. This spectrum sensing supports the Cognitive Radio users to adjust with the environment by identifying the white/vacant spaces without creating any interference to the primary user communication. The traditional filters such as Finite Impulse Response (FIR) filters and median filters used in the spectrum sensing obtains high area utilization in Cognitive Radio. In order to overcome this, an Adaptive Absolute SCORE (AAS) technique is developed based on the FIR for improving the sensing function and radio sensitivity. The area and frequency of the AAS are enhanced by using the Wallace tree multiplier (WTM) and Ladner-Fischer Adder (LFA) in the design of the FIR. The proposed architecture used for the spectrum sensing is named as AAS-WTM-LFA. This AAS-WTM-LFA architecture is developed in the Xilinx tool for different Virtex devices. The performance of AAS-WTM-LFA is analyzed in terms of LUT, slices, flip flops, bonded Input and Output Block (IOB), frequency and power. Additionally, the quality of signal processed through the AAS-WTM-LFA architecture is analyzed as Bit Error Rate (BER) and False Acceptance Rate (FAR). Additionally, the AAS-WTM-LFA architecture is compared with ACS, AAS, AAS-CSLA, AAS-R8-CSA and AASR8-CSLA. The number of LUT for AAS-WTM-LFA architecture is 247 for Spartan 6 device, that is less when compared to the remaining architectures.

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“…The authors in [22] have highlighted the benefits of using SoC devices for real-time RF analytics, and they have also presented an FPGA implementation design for a deep learning algorithm. The authors in [23] have presented a hardware design for a spectrum sensor for next generation LTE-A wireless networks.…”

Section: Related Literaturementioning

confidence: 99%

FPGA-Assisted Real-Time RF Wireless Data Analytics System: Design, Implementation, and Statistical Analyses

Khan

Lehtomäki

2020

IEEE Access

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A wide range of new ultra reliable low latency communication (URLLC) applications in next generation (NG) wireless systems demand real-time radio frequency (RF) data analytics of channel utilization (CU) that can help in making proactive resource allocation decisions. However, such real-time RF data analytics require processing of tens of millions of in-phase and quadrature (IQ) samples per second and sending huge quantities of samples to a resource allocating entity is not practical. We present design and implementation of an RF data analytics system which utilizes field-programmable gate arrays (FPGAs) at the network edge to process real-time streaming IQ samples from RF transceiver. FPGAs process millions of samples per second and output low-overhead descriptive statistics of wireless CU, such as mean CU values, maximum CU values, and entire histograms to obtain probability distribution of CU values, to a resource controller server where a quantile estimation based technique is used to detect congestion in CU in real-time. The FPGA-based modules are implemented on Xilinx's Zynq-7000 devices mounted with RF transceivers. We evaluate the performance of the implemented analytics system using extensive measurements, testing, and statistical analyses that are performed in both laboratory and over-the-air environments.

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Hardware implementation and VLSI design of spectrum sensor for next‐generation LTE‐A cognitive‐radio wireless network

Cited by 14 publications

References 26 publications

Truncation Multiplier‐Based Cognitive Radio Spectrum Analyzer for Nanomedical Applications

Truncation Multiplier‐Based Cognitive Radio Spectrum Analyzer for Nanomedical Applications

FPGA Implementation of Adaptive Absolute SCORE Algorithm for Cognitive Radio Spectrum Sensing with WTM and LFA

FPGA-Assisted Real-Time RF Wireless Data Analytics System: Design, Implementation, and Statistical Analyses

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