Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

Abstract

The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance, the clipping is still a bottleneck of any graphical system. Therefore, its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA). The designed hardware unit consists of two parts: the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the designed unit is capable of clipping (232524) line segments per second.

A Brief Survey of Clipping and Intersection Algorithms with a List of References (including Triangle-Triangle Intersections)

“…Some additional modifications of algorithms were published in Brackenbury (1984), Chao et al (2009), Cheng and Yen (1989), Dimri (2015), Dimri et al (2022), Elliriki et al (2019), Hattab and Yusof (2014), Iraji et al (2011), Jiang and Han (2013), Jianrong (2006), Kumar and Awasthi (2011), Kuzmin (1995), Li et al (2014), Li and Lei (2012), Meriaux (1984), Molla et al (2003), Nisha (2017bNisha ( , 2017a, Sobkow et al (1987), Sharma and Manohar (1993), Wang et al (1998aWang et al ( , 1998bWang et al ( , 2012Wang et al ( , 2001, Yang (1988), Pandey and Jain (2013), Bhuiyan (2009). The hardware FPGA implementation was proposed in Dawod (2011).…”