Hardware Implementation of Montgomery Modular Multiplication Based on New Compressor-4:2 Design

Abstract

Modular Multiplication (MM) plays a crucial role in public key cryptography and random numbers generation. Montgomery Modular Multiplication (MMM) Algorithm is the most popular method used for performing this operation. Currently, there are various Field Programmable Gate Array (FPGA)-based optimizations targeting the MMM implementation. However, many of these works suffer from complex critical path where multiplications and carry propagate additions are calculated at each clock cycle. This leads to a low computation throughput and limited frequency. This paper presents an efficient FPGA implementation of the MMM algorithm using compressors-4:2 (Comp-4:2s). Our objective is to realize a Hardware (HW) architecture which presents a best trade-off between computation throughput and occupied area. The execution performances of the MMM depend on both parameters: the radix-r and the modulus size. In fact, when the radix increases, the algorithm requires multiplications of form digits[Formula: see text][Formula: see text][Formula: see text]operands. On the other hand, when a long modulus is used, the HW implementation of the MMM needs long carry propagation paths. In this work we propose an approach to circumvent the required multiplications by decomposing the digits into coefficients powers of 2. Then, the multiplications are carried out by simple shifts and additions. The Carry Save Adders (CSAs) are employed to avoid the use of long carry chains. However, the combination of CSAs and the used radixes requires four-input adders. Our implementation is based on using the Comp-4:2s for the realization of regular CSAs structures. The challenge consists in the development of an optimized Comp-4:2 which must be completely integrated in single FPGA Slice. Our implementation solution allows the achievement of high computation throughput. The obtained critical path delay is independent of the operand size. The implementation on Virtex-7 circuit using a modulus of 1024-bit size shows that the MMM run in 1.31 and requires 2342 Slices.