Hardware implementations of an image compressor for mobile communications

Akter, Masuma; Reaz, Mamun Bin Ibne; Mohd-Yasin, F.; Choong, F.

doi:10.1134/s106422690808007x

Cited by 20 publications

(12 citation statements)

References 13 publications

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“…Depth-first search approaches [13]- [15] implement a regular SPIHTlike coder but the coding efficiency also decreases. An alternative scan order based upon Morton Order is used in [16]- [20]. Though, they provide less trade-off between rate and image quality, loss in image quality is still a problem.…”

Section: Related Workmentioning

confidence: 99%

“…To reduce buffer size for these coefficients, one can apply strip-based wavelet image compression [2]- [4] or image partition [5]. Second, one can apply induction methods [7]- [9] or simplification methods [10]- [20] to reduce the memory requirement for maintaining three lists. In this paper, we focus on reducing the memory capacity for maintaining three lists.…”

Section: Related Workmentioning

confidence: 99%

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A Fast and Memory Efficient SPIHT Image Encoder

Chen

2010

IEICE Trans. Inf. & Syst.

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SUMMARYSet-partitioning in hierarchical trees (SPIHT) is one of the well-known image compression schemes. SPIHT offers an agreeable compression ratio and produces an embedded bit-stream for progressive transmission. However, the major disadvantage of SPIHT is its large memory requirement. In this paper, we propose a memory efficient SPIHT image coder and its parallel implantation. The memory requirement is reduced without sacrificing image quality. All bit-planes are concurrently encoded in order to speed up the entire coding flow. The result shows that the proposed algorithm is roughly 6 times faster than the original SPIHT. For a 512 × 512 image, the memory requirement is reduced from 5.83 Mb to 491 Kb. The proposed algorithm is also realized on FPGA. With pipeline design, the circuit can run at 110 MHz, which can encode a 512×512 image in 1.438 ms. Thus, the circuit achieves very high throughput, 182 MPixels/sec, and can be applied to high performance image compression applications. key words: image coding, wavelet, set-partition in hierarchical trees (SPIHT), FPGA

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

A Fast and Memory Efficient SPIHT Image Encoder

Chen

2010

IEICE Trans. Inf. & Syst.

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“…FPGA has the merits of shorter design, higher density and lower cost cycle from the point of computer-aided design (Choong et al, 2005;Akter et al, 2008;ElGizawy et al, 2010). It comprises of a wide variety of building blocks.…”

Section: Introductionmentioning

confidence: 99%

Hardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering Applications

Amin

Mamun²,

Rahman

2011

American Journal of Applied Sciences

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Problem statement: Finite Impulse Response (FIR) filters are widely used in various DSP applications. The design of digital FIR filters is a very basic problem in digital signal processing. A FIR filter with multiple operation capability is certainly very useful for any real-time filtering applications. This article presents a multipurpose FIR filter design modeled by the hardware description language VHDL for real-time filtering application. Approach: The VHDL has its concept of concurrency to cope with the parallelism of digital hardware. The novel feature is the capability of the design to accomplish up to 127variable filter order and an arbitrary filter frequency response. The coefficients are calculated by Hamming windowing technique. Basing on selection embedded in the design, the model is able to execute highpass, lowpass, bandstop and bandpass filtering operations. It is set at 8-bit signed data processing. To filter the input data in time domain, Linear Constant Coefficient Difference Equation (LCCDE) is used by the filter. Results: The design outputs are validated through simulation and compilation. The output results are also compared with the MATLAB implemented calculated output results to test the correctness that proves the effectiveness of the design. Conclusion: With the capability of filtering signal in real time mode utilizing arbitrary filter shape, the multipurpose filter proves to be versatile.

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“…From the perspective of computer-aided design, FPGA comes with the merits of lower cost, higher density and shorter design cycle (Choong et al, 2005;Akter et al, 2008;Reaz et al, 2011b). It comprises a wide variety of building blocks.…”

Section: Introductionmentioning

confidence: 99%

Single Core Hardware Module to Implement Boolean Function Classification Techniques

Marufuzzaman

Mamun²,

Hashim³

et al. 2011

American Journal of Applied Sciences

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Problem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was performed by incorporating Boolean function classification into Huffman coding. This allows compression that was more efficient because the data had been categorized and simplified before the encoding was done. Simulation, timing analysis and circuit synthesis were commenced to verify the functionality and performance of the designated circuits which supports the practicality, advantages and effectiveness of the proposed single core hardware implementation. Results: The result shows a higher compression ratio. The average compression ratio was 25-37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz. Conclusion: The hardware implementation demonstrated complete, correct functionality and met all the initial system requirements.

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Hardware implementations of an image compressor for mobile communications

Cited by 20 publications

References 13 publications

A Fast and Memory Efficient SPIHT Image Encoder

A Fast and Memory Efficient SPIHT Image Encoder

Hardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering Applications

Single Core Hardware Module to Implement Boolean Function Classification Techniques

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