Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain

Abstract

Fruit-80, which emerged as an ultra-lightweight stream cipher with 80-bit secret key, is oriented toward resource constrained devices in the Internet of Things. In this paper, we propose area and speed optimization architectures of Fruit-80 on FPGAs. Our implementations include both serial and parallel structure and optimize area, power, speed and throughput respectively. The area optimization architecture aims to achieve the most suitable ratio of look-up-tables and flip-flops to fully utilize the reconfigurable unit. It also reuses NFSR and LFSR feedback functions to save resources for high throughput. The speed optimization architecture adopts a hybrid approach for parallelization and reduces the latency of long data paths by pre-generating primary feedback and inserting flip-flops. Besides, we recommend using the round key function to optimize serial or parallel implementations for Fruit-80 and using indexing and shifting methods for different throughput. In conclusion, our results show that the area optimization architecture occupies up to 35 slices on Xilinx Spartan-3 FPGA and 18 slices on Xilinx 7 series FPGA, smaller than that of Grain and other common stream ciphers. The optimal throughput/area ratio of the speed optimization architecture is 7.74 Mbps/ slice, better than that of Grain v1, which is 5.98 Mbps/ slice. The serial implementation of Fruit-80 with round key function occupies only 75 slices on Spartan-3 FPGA. To the best of our knowledge, the result sets a new record of the minimum area in lightweight cipher implementation on FPGA.

Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher

“…Compared to the existing architectures, the utilization of LUTs and slices is reduced by 66.05% and 68.40% with respect to [22], 84.01% and 91.95% with respect to [13], 43.29% and 14.84% with respect to [33] and 47.56% with respect to [25]. The proposed TinyJAMBU-128 architecture has maximum frequency, F max of 128.15 MHz, which is better than [33] and [25].…”

“…Compared to the existing architectures, the utilization of LUTs and slices is reduced by 66.05% and 68.40% with respect to [22], 84.01% and 91.95% with respect to [13], 43.29% and 14.84% with respect to [33] and 47.56% with respect to [25]. The proposed TinyJAMBU-128 architecture has maximum frequency, F max of 128.15 MHz, which is better than [33] and [25]. Compared to the existing architectures implemented on the Virtex-7 FPGA device, the power usage of the proposed work is reduced by 87.41% with respect to [25] and 90.27% with respect to [22].…”

“…An implementation of the proposed architecture has been performed on the Virtex-7 FPGA device, illustrating better utilization of LUT, slices and power consumption than existing architectures. The LUTs and slices are reduced by 66.05% and 68.40% with respect to [22], 84.01% and 91.95% with respect to [13], 43.29% and 14.84% with respect to [33] and 47.56% with respect to [25]. The power consumption is reduced by 87.41% with respect to [25] and 90.27% with respect to [22].…”

Threats, Attacks, and Cryptography Frameworks of Cybersecurity in Critical Infrastructures

“…Other published research papers develop a unified architecture of PUFs and TRNGs with the purpose of enhancing the compactness, scalability, flexibility, and reconfigurability of the system while increasing the security and privacy [68,69]. Lightweight or accelerated versions of block ciphers and stream ciphers are also developed for more efficient encryption/decryption of data and authentication policies [70][71][72][73]. Lastly, a novel authentication scheme has been developed by the research community, named Privacy-Preserving Mutual Authentication (PPMA).…”