Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms

Sirkunan, Jeevan; Ooi, Chia Yee; Shaikh-Husin, Nasir; Hau, Yuan Wen; Marsono, Muhammad Nadzir

doi:10.1016/j.sysarc.2016.12.006

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Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms

Cited by 3 publications

References 28 publications

A configurable multiplex data transfer model for asynchronous and heterogeneous FPGA accelerators on single DMA device

A configurable multiplex data transfer model for asynchronous and heterogeneous FPGA accelerators on single DMA device

A few open problems and solutions for software technologies for dependable distributed systems

Providing QoS in contention management for software transactional memory

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