Hardware Transactional Memory Supporting I/O Operations within Transactions

Abstract

I/O operation within transactions is one of thechallenges for hardware transactional memory. This paper analyses the problem of I/O operations within transactions, and proposes a hardware transactional memory system architecture based on multi-core processor and current cache coherent mechanisms. The system supports execution of transactions by adding transactional buffer and related hardware and software. I/O operations within transactions are implemented by partial commit based on commit-lock, and blocking / waking-up of transactional threads. The solution solves or avoids the problems that I/O operations within transactions faced, including rollback, transaction migration and transactional buffer overflow. The system has been implemented by simulation. Its performance is evaluated by five benchmark applications. Simulation results show that the transactional programs executed in our system outperformed traditional lock-based programs.