Hardware Trojan attacks in embedded memory

Hoque, Tamzidul; Wang, Xinmu; Basak, Abhishek; Karam, Robert; Bhunia, Swarup

doi:10.1109/vts.2018.8368630

Cited by 26 publications

(8 citation statements)

References 8 publications

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“…As sensitive information leakage is one of the primary rationales behind HT attacks, designers are leaning towards the memory/storage level Trojan insertion to decrypt critical data. Authors in [49] inserted two versions of HTs into an SRAM array in the design phase. The proposed stealthy design can successfully evade the testing phase.…”

Section: F Memory/storage Unitmentioning

confidence: 99%

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

Dhavlle

Hassan

Mittapalli

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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The ever-increasing demand for sophisticated cyberphysical systems (CPS), combined with the fabless model, led to vulnerability exploits in the IC supply chain, especially the insertion of hardware Trojans (HTs). The HTs are malicious modifications made to an authentic design to disrupt the functioning of the integrated circuits (ICs). In this work, we present a survey of the state-of-the-art HT designs focusing on the Trojan design, the risk level in the supply chain, and the targeted platform, followed by a discussion based on our observations. We categorize the HT designs based on the targeted platforms such as ML accelerators, IoT devices, FPGAs, ASICs, memory devices, CPU, and Cryptographic cores.

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Section: F Memory/storage Unitmentioning

confidence: 99%

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

Dhavlle

Hassan

Mittapalli

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…There are still few studies on Trojan attacks in embedded memory. Hoque et al [159] discuss a new hardware Trojan for embedded SRAM arrays. They demonstrate various types of Trojan circuits in SRAM including resistive short, bridge, and open in circuit nodes.…”

Section: Hardwarementioning

confidence: 99%

A Survey on RISC-V Security: Hardware and Architecture

2021

Preprint

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The Internet of Things (IoT) is an ongoing technological revolution. Embedded processors are the processing engines of smart IoT devices. For decades, these processors were mainly based on the Arm instruction set architecture (ISA). In recent years, the free and open RISC-V ISA standard has attracted the attention of industry and academia and is becoming the mainstream. Many companies have already owned or are designing RISC-V processors. Many important operating systems and major tool chains have supported RISC-V. Data security and user privacy protection are common challenges faced by all IoT devices. In order to deal with foreseeable security threats, the RISC-V community is studying security solutions aimed at achieving a root of trust (RoT) and ensuring that sensitive information on RISC-V devices is not tampered with or leaked. Many RISC-V security research projects are underway, but the academic community has not yet conducted a comprehensive survey of RISC-V security solutions. The latest technology and future development direction of RICS-V security research are still unclear. In order to fill this research gap, this paper presents an in-depth survey on RISC-V security technologies. This paper summarizes the representative security mechanisms of RISC-V hardware and architecture. Specifically, we first briefly introduce the background and development status of RISC-V, and compare the RISC-V mechanisms with the most relevant Arm mechanisms, highlighting their similarities and differences. Then, we investigate the security research of RISC-V around the theme of hardware and architecture security. Our survey covers hardware and physical access security, hardware-assisted security units, ISA security extensions, memory protection, cryptographic primitives, and side-channel attack protection. Based on our survey, we predict the future research and development directions of RISC-V security. We hope that our research can inspire RISC-V researchers and developers.CCS Concepts: • Security and privacy → Embedded systems security; Cryptography.

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“…HTs that could be inserted into the GDS-II files of an SoC by a malicious foundry in order to leak data or cause faults in DRAMs were proposed in [3]. HTs that can perform post-deployment data tampering in SRAMs and that can leak sensitive data out of NVM cells were introduced in [4] and [5], respectively. However, denial of service HTs have not been explored extensively in the context of memories and DRAMs.…”

Section: Motivation and Related Workmentioning

confidence: 99%

Detecting denial-of-service hardware Trojans in DRAM-based memory systems

Salem

Topham

2021

2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)

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DRAM latencies are inherently variable, potentially allowing a denial-of-service hardware Trojan (DoS HT) to degrade memory performance without becoming immediately obvious. This paper addresses the challenge of detecting a DoS HT that may have been inserted into a DRAM-based memory system, without requiring detailed internal knowledge of the DRAM device. We present a real-time machine-learning based DoS HT detection technique based on a low-cost hardware monitor at the interface to the DRAM controller, coupled with periodic software based analysis of monitoring output.

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Hardware Trojan attacks in embedded memory

Cited by 26 publications

References 8 publications

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey

A Survey on RISC-V Security: Hardware and Architecture

Detecting denial-of-service hardware Trojans in DRAM-based memory systems

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