Heterogeneous built-in resiliency of application specific programmable processors

Kim, K.; Karri, R.; Potkonjak, M.

doi:10.1109/iccad.1996.569830

“…In particular, a great deal of effort has been made in combining retargetable compilation technologies and design of instruction sets [22]- [26]. Several research groups have published results on the topic of selecting and designing instruction set and processor architecture for a particular application domains [27], [28].…”

Section: Related Work and Our Contributionsmentioning

confidence: 99%

Exploring the diversity of multimedia systems

Kin¹,

Lee

²

,

Mangione-Smith

³

et al. 2001

IEEE Trans. VLSI Syst.

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Abstract-We evaluate the validity of the fundamental assumption behind application-specific programmable processors: that applications differ from each other in key parameters which are exploitable, such as the available instruction-level parallelism (ILP), demand on various hardware resources, and the desired mix of function units. Following the tradition of the CAD community, we develop an accurate chip area estimate and a set of aggressive hardware optimization algorithms. We follow the tradition of the architecture community by using comprehensive real-life benchmarks and production quality tools. This combination enables us to build a unique framework for system-level synthesis and to gain valuable insights about design and use of application-specific programmable processors for modern applications. We explore the application-specific programmable processor (ASSP) design space to understand the relationship between performance and area. The architecture model we used is the Hewlett Packard PA-RISC [1] with single level caches. The system, including all memory and bus latencies, is simulated and no other specialized ALU or memory structures are being used. The experimental results reveal a number of important characteristics of the ASSP design space. For example, we found that in most cases a single programmable architecture performs similarly to a set of architectures that are tuned to individual application. A notable exception is highly cost sensitive designs, which we observe need a small number of specialized architectures that require smaller areas. Also, it is clear that there is enough parallelism in the typical media and communication applications to justify use of high number of function units. We found that the framework introduced in this paper can be very valuable in making early design decisions such as area and architectural configuration tradeoff, cache and issue width tradeoff under area constraint, and the number of branch units and issue width.Index Terms-Application-specific programmable processor, instruction level parallelism, mediabench, mediaprocessor, system-level synthesis.

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“…In particular, a great deal of effort has been made in combining retargetable compilation technologies and design of instruction sets [1,21,22,23,30]. Several research groups have published results on the topic of selecting and designing instruction set and processor architecture for particular application domains [18,33].…”

Section: Related Work and Our Contributionsmentioning

confidence: 99%

Media architecture

Lee¹,

Kin²,

Potkonjak

³

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to synthesize a high performance machine for an application. Using the framework we evaluate the validity of the fundamental assumption behind the development of application-specific programmable processors. Application-specific processors are based on the idea that applications differ from each other in key architectural parameters, such as the available instruction-level parallelism, demand on various hardware components (e.g. cache memory units, register files) and the need for different number of functional units. We found that the framework introduced in this paper can be valuable in making early design decisions such as area and architectural trade-off, cache and instruction issue width trade-off under area constraint, and the number of branch units and issue width.

show abstract

“…In particular, a great deal of effort has been made in combining retargetable compilation technologies and design of instruction sets [1,21,22,23,30]. Several research groups have published results on the topic of selecting and designing instruction set and processor architecture for particular application domains [18,33].…”

Section: Related Work and Our Contributionsmentioning

confidence: 99%

Media architecture: general purpose vs. multiple application-specific programmable processor

Lee¹,

Kin²,

Potkonjak³

et al.

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

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In this paper we report a framework that makes it possible for a designer to rapidly explore the application-specific programmable processor design space under area constraints. The framework uses a production-quality compiler and simulation tools to synthesize a high performance machine for an application. Using the framework we evaluate the validity of the fundamental assumption behind the development of application-specific programmable processors. Application-specific processors are based on the idea that applications differ from each other in key architectural parameters, such as the available instruction-level parallelism, demand on various hardware components (e.g. cache memory units, register files) and the need for different number of functional units. We found that the framework introduced in this paper can be valuable in making early design decisions such as area and architectural trade-off, cache and instruction issue width trade-off under area constraint, and the number of branch units and issue width.

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Heterogeneous built-in resiliency of application specific programmable processors

Cited by 7 publications

References 12 publications

Exploring the diversity of multimedia systems

Exploring the diversity of multimedia systems

Media architecture

Media architecture: general purpose vs. multiple application-specific programmable processor

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