Heuristic and Statistical Power Estimation Model for FPGA Based Wireless Systems

Verma, Gaurav; Singhal, Tarun; Kumar, Rahul; Chauhan, Sunita; Shekhar, Sushant; Pandey, Bishwajeet; Hussain, Dil Muhammad Akbar

doi:10.1007/s11277-018-5927-7

Cited by 7 publications

(3 citation statements)

References 11 publications

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“…In [150] two techniques are proposed by Verma et al remarking the importance of predicting the power consumption in an early stage of the accelerator design: a heuristic approach based on a backpropagation neural network and a regression based on statistics.…”

Section: ) Modelsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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Hardware accelerators based on field programmable gate array (FPGA) and system on chip (SoC) devices have gained attention in recent years. One of the main reasons is that these devices contain reconfigurable logic, which makes them feasible for boosting the performance of applications. High-level synthesis (HLS) tools facilitate the creation of FPGA code from a high level of abstraction using different directives to obtain an optimized hardware design based on performance metrics. However, the complexity of the design space depends on different factors such as the number of directives used in the source code, the available resources in the device, and the clock frequency. Design space exploration (DSE) techniques comprise the evaluation of multiple implementations with different combinations of directives to obtain a design with a good compromise between different metrics. This paper presents a survey of models, methodologies, and frameworks proposed for metric estimation, FPGA-based DSE, and power consumption estimation on FPGA/SoC. The main features, limitations, and trade-offs of these approaches are described. We also present the integration of existing models and frameworks in diverse research areas and identify the different challenges to be addressed. INDEX TERMSComputing models, design space exploration, field programmable gate array (FPGA), system on chip (SoC), power consumption.years (2016-2022) and have been selected based on the topics addressed in this survey. Several papers published before 2016 have been considered because of their contributions to the current literature. C. OUTLINEThe remainder of this paper is organized as follows. Section II briefly presents the most widely used parallel computing models for CPU, GPU, and multicore processors. Section III introduces the FPGA-based reconfigurable hardware accelerator architectures, hardware/software co-design, DSE and metrics, and the techniques to improve latency, area, and power for this technology. In Section IV, we describe previous works on models, methodologies, and frameworks proposed for FPGA/SoC according to their main features: metrics estimation (IV-A), FPGA-based DSE (IV-B), and power consumption estimation (IV-C); and in Section IV-D, we present a summary and discussion. The integration of models and frameworks for FPGA-based reconfigurable hardware accelerators in different research fields is exposed in Section V. Challenges are analyzed in Section VI. Finally, conclusions are presented in Section VII. II. PARALLEL COMPUTING MODELS FOR PERFORMANCE ESTIMATIONComputing models allow to easily analyzing algorithms by simplifying the computational world to a reduced set of parameters that define the cost of arithmetic and memory access operations and communication. These models contribute to the search for efficient algorithms for a given architecture, improving the productivity of designers, programmers, and engineers. A small amount of communication, a small number of operations, and a high degree of parallelism are key points that d...

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Section: ) Modelsmentioning

confidence: 99%

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

et al. 2022

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“…Random access memory (ROM) architecture for Virtex-6 FPGA was interfaced in [26]. In [27], researchers have used FPGA device to design a low power model for wireless data communication. In [28], researchers used energy-efficient techniques such as scaling the capacitance value of the capacitor of output load to design a green communication model of FIR Filter.…”

Section: Introductionmentioning

confidence: 99%

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

Shrivastava¹,

Rizwan

Kumar

et al. 2021

Wireless Communications and Mobile Computing

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The issue of the energy shortage is affecting the entire planet. This is occurring because of massive population and industry growth around the world. As a result, the entire world is attempting to implement green networking systems and manufacture the power/energy efficient products. This research work discusses the green networking system technologies. This work introduces a power-efficient control unit (CU) design and implemented on the Zynq SoC (System on Chip) ultrascale field programmable gate array (FPGA). The VIVADO HLx Design Suite is used to simulate and analyze the CU model which is considered as one of the key components of central processing unit (CPU), used for data communication purposes. The CU is made suitable for the green communication by making it power-efficient. Therefore, the power consumption of the CU is analyzed for the various set frequency value ranging between 100 MHz and 5 GHz, and it is discovered that as the clock frequency rises up, the total power consumption also tends to get increased. The total power of the proposed model is reduced by 77.42%, 21.29%, and 17.93% from three models, respectively, being compared in the present paper. Final results shows that the CU is better suited to run at low frequencies to optimize power consumption.

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“…So, designing of a complete system for power estimation at this level can be a virtuous choice. Numerous models have been established in the literature for power estimation of individual blocks, but very few literatures are available for power estimation of different applications designed using IP cores [2], [17].…”

Section: Introductionmentioning

confidence: 99%

Power Estimation of QPSK and BPSK Modulation Systems for FPGAs based on IP Modeling for Wireless Applications

Singh

Verma

Khare

2021

Preprint

Self Cite

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FPGA market has expanded due to its adoption in mobile phones and wearable devices. The communication IP blocks in Field Programmable Gate Array (FPGAs) has made it possible to realize different communication systems. However, in spite of their high performance, FPGAs suffers from high power consumption due to their complex architecture as compared to their ASIC counterpart. This has made power estimation as an important design metric. The existing commercial tools provide the option to estimate the power, but at the cost of longer estimation time as the designs have to follow the complete design cycle. Moreover, literature, mostly focuses on power estimation of individual blocks and power estimation of the complete system is still in infancy stage. Therefore, in this work, Quadrature Phase Shift Keying (QPSK) and Binary Phase Shift Keying (BPSK) modulation systems have been designed that are used in various wireless and satellite communication applications. Further, a new identity is proposed that could evaluate the power of whole system. The QPSK and BPSK systems have been designed via embedded IP and user-defined IP cores. A power estimation model of diverse blocks of QPSK and BPSK modulation systems have been developed based on a supervised machine learning technique using MATLAB R2016b and models are validated against commercial tool. Finally, the power of complete QPSK and BPSK modulation system is estimated using the proposed identity and is also validated for accuracy with reference to Vivado 2014.2 tool targeted to the Zynq family device and state of the art work. It has been seen from the results that the proposed identity outperforms in power estimation of complete systems as compared to existing identities available in literature and is providing aligned results with reference to the commercial tool.

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Heuristic and Statistical Power Estimation Model for FPGA Based Wireless Systems

Cited by 7 publications

References 11 publications

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks

VLSI Implementation of Green Computing Control Unit on Zynq FPGA for Green Communication

Power Estimation of QPSK and BPSK Modulation Systems for FPGAs based on IP Modeling for Wireless Applications

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