Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems

Abstract

We present a hierarchical address-event routing (HiAER) architecture for scalable communication of neural and synaptic spike events between neuromorphic processors, implemented with five Xilinx Spartan-6 field-programmable gate arrays and four custom analog neuromophic integrated circuits serving 262k neurons and 262M synapses. The architecture extends the single-bus address-event representation protocol to a hierarchy of multiple nested buses, routing events across increasing scales of spatial distance. The HiAER protocol provides individually programmable axonal delay in addition to strength for each synapse, lending itself toward biologically plausible neural network architectures, and scales across a range of hierarchies suitable for multichip and multiboard systems in reconfigurable large-scale neuromorphic systems. We show approximately linear scaling of net global synaptic event throughput with number of routing nodes in the network, at 3.6×10 synaptic events per second per 16k-neuron node in the hierarchy.

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning

“…We refer to this as a single NSAT tile. Note that such tiled architecture has been proposed earlier in the context of neuromorphic hardware with multi-tile communication enabled through a hierarchical AER communication fabric (Park et al, 2017). The contribution of this work therefore focused on specifics of the digital implementation inside each tile.…”

“…Extreme efficiency in data-driven autonomy hinges on the establishment of (i) energy-efficient computational building blocks and (ii) algorithms that build on these blocks. NSAT is a spiking neural network architecture designed on these assumptions, using neural building blocks that are constructed from algorithmic principles and an event-based architecture that emphasizes locally dense and globally sparse communication (Park et al, 2017). …”

MorphIC: A 65-nm 738k-Synapse/mm$^2$ Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning

“…no dedicated access to a stored mapping table). This contrasts with Neurogrid [25] and HiAER [23], which achieve low-cost largescale routing at the expense of requiring external mapping table storage, thus indirectly inducing high resource and power overheads. SpiNNaker [24], [35] embeds the largest-scale multicast connectivity infrastructure proposed so far.…”

“…The latter aspect can be mitigated by a controller update, similarly to the crossbar optimization with start and end addresses proposed in Section IV-C for fully-connected layers. Finally, it is worth noting that all the routers in the aforementioned approaches operate asynchronously, except in HiAER [23] and MorphIC. In MorphIC, the choice of clocked operation for the routers allows for a straightforward design at the expense of efficiency.…”

Data and Power Efficient Intelligence with Neuromorphic Learning Machines

“…On a platform supporting only spike-based communication, this information must be encoded in spikes. On the other hand, dashed edges crossing domains can be handled through efficient address-event communication protocols, such as in hierarchical AER (HiAER) (Park et al., 2017). In this example, the synthesized learning subgraph (red nodes and edges) is consistent with eRBP, via a random matrix G 0 .…”