Hierarchical scheduling in high level synthesis using resource sharing across nested loops

Ghosh, Amit B.; Lodha, S.K.; Vemuri, R.

doi:10.1109/glsv.1999.757396

Cited by 2 publications

(1 citation statement)

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“…Path-based scheduling [Camposano 1991] list-schedule each execution path separately and then combine the schedules using goto operations. Ghosh et al [1999] describes an hierarchical variant of LS targeting compound loops. The goal is to share resources between the schedules of different subloops.…”

Section: Related Workmentioning

confidence: 99%

The benefits of using variable-length pipelined operations in high-level synthesis

Ben-Asher

Rotem

2013

ACM Trans. Embed. Comput. Syst.

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Current high-level synthesis systems synthesize arithmetic units of a fixed known number of stages, and the scheduler mainly determines when units are activated. We focus on scheduling techniques for the high-level synthesis of pipelined arithmetic units where the number of stages of these operations is a free parameter of the synthesis. This problem is motivated by the ability to automatically create pipelined functional units, such as multipliers, with different pipe lengths. These units have different characteristics in terms of parallelism level, clock latency, frequency, etc. This article presents the Variable-length Pipeline Scheduler (VPS). The ability to synthesize variable-length pipelined units expands the known scheduling problem of high-level synthesis to include a search for a minimal number of hardware units (operations) and their desired number of stages. The proposed search procedure is based on algorithms that find a local minima in a d-dimensional grid, thus avoiding the need to evaluate all possible points in the space. We have implemented a C language compiler for VPS targeting FPGAs. Our results demonstrate that using variable-length pipeline units can reduce the overall resource usage and improve the execution time when synthesized onto an FPGA. The proposed search is sufficiently fast, taking only a few seconds, allowing an interactive mode of work. A comparison with xPilot shows a significant saving of hardware resources while maintaining comparable execution times of the resulting circuits. This work is an extension of a previous paper [Ben-Asher and Rotem 2008]

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Section: Related Workmentioning

confidence: 99%