Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Results

Lorenz, J.; Bär, E.; Clees, Tanja; Evanschitzky, Peter; Jancke, Roland; Kampen, C.; Paschen, Uwe; Salzig, Christian; Selberherr, S.

doi:10.1109/ted.2011.2150226

Cited by 21 publications

(9 citation statements)

References 8 publications

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“…However, since different values of the six process variations considered lead to the same value of the gate length and particularly because the peak annealing temperature is varied as well, a spread of the READ static noise margin for the constant gate length is also observed. For more explanations and results, see [2].…”

Section: Hierarchical Simulation Of Variabilitymentioning

confidence: 99%

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Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Lorenz

Bär

Clees

et al. 2011

IEEE Trans. Electron Devices

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Abstract-Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology.

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Section: Hierarchical Simulation Of Variabilitymentioning

confidence: 99%

“…An approach for the hierarchical simulation of variations including their correlations, developed at Fraunhofer, is presented. Application results are shown in another paper included in this Special Issue [2].…”

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confidence: 99%

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Lorenz

Bär

Clees

et al. 2011

IEEE Trans. Electron Devices

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“…These variations can be lumped into two categories: static and dynamic. Static variations, primarily process variations [1], do not change over time and typically affect the worst-case path of each die. Dynamic variations, such as changes in temperature [2][3][4][5], voltage [2][3][4][5], and aging [6], change over time and require in-situ methods to combat degradation of performance.…”

Section: Sources Of Variation In Cmos Circuitsmentioning

confidence: 99%

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

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Krimer

Moezzi-Madani

et al. 2011

JLPEA

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While Moore's law scaling continues to double transistor density every technology generation, new design challenges are introduced. One of these challenges is variation, resulting in deviations in the behavior of transistors, most importantly in switching delays. These exaggerated delays widen the gap between the average and the worst case behavior of a circuit. Conventionally, circuits are designed to accommodate the worst case delay and are therefore becoming very limited in their performance advantages. Thus, allowing for an average case oriented design is a promising solution, maintaining the pace of performance improvement over future generations. However, to maintain correctness, such an approach will require on the fly mechanisms to prevent, detect, and resolve violations. This paper explores such mechanisms, allowing the improvement of circuit performance under intensifying variations. We present speculative error detection techniques along with recovery mechanisms. We continue by discussing their ability to operate under extreme variations including sub-threshold operation. While the main focus of this survey is on circuit J. Low Power Electron. Appl. 2011, 1 335 approaches, for its completeness, we discuss higher-level, architectural and algorithmic techniques as well.

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“…Whereas the impact of statistical variations such as Random Dopant Fluctuations (RDF), Metal Gate Granularity (MGG), and Line Edge Roughness (LER) have been frequently and since long discussed in the literature (e.g., in [3,4,5]), the effects of systematic process variations have so far got much less attention. Some publications with involvement of authors of this paper referred to bulk transistors [1,6,7,8,9]. Two examples for the impact of patterning processes on FinFET transistors were presented earlier [10,11,12], in the latter case also discussing the impact on a static random-access memory (SRAM) cell.…”

Section: Introductionmentioning

confidence: 99%

Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

et al. 2018

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Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated.

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Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Results

Cited by 21 publications

References 8 publications

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Hierarchical Simulation of Process Variations and Their Impact on Circuits and Systems: Methodology

Error Detection and Recovery Techniques for Variation-Aware CMOS Computing: A Comprehensive Review

Process Variability—Technological Challenge and Design Issue for Nanoscale Devices

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