High Efficiency, Good phase linearity 0.18 µm CMOS Power Amplifier for MBAN-UWB Applications

Abstract

This paper presents the design of 3.1-10.6 GHz class AB power amplifier (PA) suitable for medical body area network (MBAN) Ultra-Wide Band (UWB) applications in TSMC 0.18 µm technology. An optimization technique to simultaneously maximize power added efficiency(PAE) and minimize group delay variation is employed. Source and Load-pull contours are used to design inter and output stage matching circuits. The post-layout simulation results indicated that the designed PA has a maximum PAE of 32 % and an output 1-dB compression of 11 dBm at 4 GHz. In addition, a small group delay variation of ± 50 ps was realized over the whole required frequency band . Moreover, the proposed PA has small signal power gain (S21) of 12.5 dB with ripple less than 1.5 dB over the frequency range between 3.1 GHz to 10.6 GHz, while consuming 36 mW.

Ultra-wideband CMOS power amplifier for wireless body area network applications: a review

“…The negative side of the cascade topology is that it has high power consumption and high silicon area due to the increase in hardware components. Several previous works employ the cascaded configuration in the design and implementation of power amplifiers in order to have high gain [11], [12], [16], [17], [21], [22], [39], [45], [48], [52], [54]- [56], [59].…”

“…There have been various works on the wideband CMOS cascaded power amplifier [11], [12], [16], [17], [21], [22], [39], [45], [48], [52], [54]- [56], [59]. A summary of the published wideband cascaded power amplifiers is presented in Table 1.…”

“…However, increasing the number of stages utilized in the power amplifier design will result in a greater increase in power consumption and area. Thus, almost all prior works have employed three-stage cascaded power amplifiers [11], [17], [39], [45], [52], [54], [59] or two-stage cascaded power amplifiers [12], [16], [21], [22], [48], [55], [56]. To increase the overall gain, prior works have employed three-stage cascaded power amplifiers.…”

“…Similarly, a common-gate stage followed by a common-source CS stage operating in the frequency bands of 3 to 7 GHz and 3.1 to 10.6 GHz has been attained in [22], [56], respectively. The input stage includes a CG transistor loaded by a diode-connected transistor to increase the first stage gain.…”

Analytical modelling of ultra‐small group delay variation of ultra‐broadband RF power amplifier using NSGA‐II algorithm

“…Many CMOS PAs have been reported in the published articles. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] One of the earliest CMOS PA presented GD variation of ±250 ps, which is too high. 1 A 3.1-6 GHz CMOS PA based on cascode amplifier with resistive shunt feedback topology offering forwarded gain (S 21 ) of 10 ± 1 dB and achieved a GD variation of ±195.5 ps.…”