High frequency common-mode noise in serdes circuits’ optimized interconnections

Abstract

According to the requirements imposed by the new four-level pulse amplitude modulation (PAM4) standard for high-speed data transfer and processing, electrical constraints and manufacturing tolerances in integrated electronic packages impose accurate electromagnetic simulations and new S-parameters analysis, saving time and financial resources for next-generation switches, routers or data centers circuits implementation. The complexity of the advanced networking class circuits' encapsulation substrates massively increases due to the large number of differential signals that it integrates. Differential signaling has replaced single-ended transmission in high-speed circuits due to their many advantages, including increased immunity to crosstalk and electromagnetic interference, but common-mode noise due to timing skew or amplitude unbalance differences can still affect them. This work tests five different models, identifies and optimizes the 45° bends, structures that commonly affect the reflections in a differential stripline. Then it studies differential transmission lines in stripline topology, implemented in a 12-layered flip-chip package, using S-parameters, inspecting and comparing the common-mode noise. In this way, the paper combines microwave theory with a real chip packaging design in an innovative way, using finite element analysis of electromagnetic field simulation and mixed-mod scattering parameters of differential topologies, towards an optimized structure design.