High-level synthesis: an essential ingredient for designing complex ASICs

Arvind, .; Nikhil, Rishiyur S.; Rosenband, Daniel L.; Dave, Nirav

doi:10.1109/iccad.2004.1382681

Cited by 46 publications

(26 citation statements)

References 11 publications

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“…Although some tools support memory accesses whose ordering dependences are statically determinable [3], [13], [19], [28]- [31], the memory-interface design is quite different from our solution. Since all memory accesses are always statically scheduled in these approaches, contention between memory accesses is statically reduced or eliminated.…”

Section: B Architecture Supportmentioning

confidence: 90%

“…Huang et al [29] rely on a platform-based architecture that obviates the need for elaborate memory-access interfaces that must support concurrence. Finally, an interesting architecture is proposed in [3]: Memory accesses flow through a flexible FIFO, which communicates with a centralized memory controller. The FIFO polls the controller to see whether a memory access is completed or not.…”

Section: B Architecture Supportmentioning

confidence: 99%

“…Although some HLS tools allow some type of memory abstraction, they all impose heavy restrictions on the use of these abstractions. For example, many HLS tools impose a fixed access latency for memory accesses [3], [5], [6]. This is usually the worst case (and often unacceptable) latency for a memory access, and, in general, all of the tools restrict the input specification to statically explicit memory dependences.…”

mentioning

confidence: 99%

“…As the increase in design productivity continues to lag behind increasing application-specific integrated circuit (ASIC) complexity [2], high-level synthesis (HLS) tools can play a central role in delivering high-performance lowpower large-scale ASICs from abstract complex behavioral specifications [3].…”

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confidence: 99%

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Hardware compilation of application-specific memory-access interconnect

Venkataramani

Bjerregaard

Chelcea

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-A major obstacle to successful high-level synthesis (HLS) of large-scale application-specified integrated circuit systems is the presence of memory accesses to a shared-memory subsystem. The latency to access memory is often not statically predictable, which creates problems for scheduling operations dependent on memory reads. More fundamental is that dependences between accesses may not be statically provable (e.g., if the specification language permits pointers), which introduces memory-consistency problems. Addressing these issues with static scheduling results in overly conservative circuits, and thus, most state-of-the-art HLS tools limit memory systems to those that have predictable latencies and limit programmers to specifications that forbid arbitrary memory-reference patterns. A new HLS framework for the synthesis and optimization of memory accesses (SOMA) is presented. SOMA enables specifications to include arbitrary memory references (e.g., pointers) and allows the memory system to incorporate features that might cause the latency of a memory access to vary dynamically. This results in raising the level of abstraction in the input specification, enabling faster design times. SOMA synthesizes a memory access network (MAN) architecture that facilitates dynamic scheduling and ordering of memory accesses. The paper describes a basic MAN construction technique that illustrates how dynamic ordering helps in efficiently maintaining memory consistency and how dynamic scheduling helps alleviate the variable-latency problem. Then, it is shown how static analysis of the access patterns can be used to optimize the MAN. One optimization changes the MAN interconnect topology to increase concurrence. A second optimization reduces the synchronization overhead necessary to maintain memory consistency. Postlayout experiments demonstrate that SOMA's application-specific MAN construction significantly improves power and performance for a range of benchmarks.Index Terms-Communication synthesis, dataflow synthesis, high-level synthesis (HLS), interface design.

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Section: B Architecture Supportmentioning

confidence: 90%

Section: B Architecture Supportmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Hardware compilation of application-specific memory-access interconnect

Venkataramani

Bjerregaard

Chelcea

et al. 2006

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Most importantly, Bluespec compiler offers the ability to synthesize high-quality circuits in a "push-button" manner. Several studies have shown that it is possible to create designs in Bluespec very quickly and once a design is working, to modify its parts to gain much deeper insights into the cost and effectiveness of sub-blocks [2,4,14].…”

Section: Introductionmentioning

confidence: 99%

H.264 Decoder: A Case Study in Multiple Design Points

Fleming

Lin

Dave

et al. 2008

2008 6th ACM/IEEE International Conference on Formal Methods and Models for Co-Design

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Abstract:H.264, a state-of-the-art video compression standard, is used across a range of products from cell phones to HDTV. These products have vastly different performance, power and cost requirements, necessitating different hardwaresoftware solutions for H.264 decoding. We show that a design methodology and associated tools which support synthesis from high-level descriptions and which allow modular refinement throughout the design cycle, can share the majority of design effort across multiple design points. Using Bluespec SystemVerilog, we have created a variety of designs for the H.264 decoder tuned to support decoding at resolutions ranging from QCIF video (176 × 144 @15 frames/second) to 1080p video (1280 × 1080)p @60 frames/second) in a 180nm process. Some of these design points require major transformations of pipelining to increase performance or to reduce area. We also explore several common design issues surrounding memory structures, such as caches and on-chip vs. off-chip memories.We believe the design methodology used in this paper is directly applicable to many IP blocks involving algorithmic specifications. The same design capabilities also permit rapid microarchitecture exploration and changes in RTL late in the design process even in non-algorithmic IP blocks.

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Related Work

Singh

Shukla

2010

Low Power Hardware Synthesis From Concurrent Action-Oriented Specifications

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High-level synthesis: an essential ingredient for designing complex ASICs

Cited by 46 publications

References 11 publications

Hardware compilation of application-specific memory-access interconnect

Hardware compilation of application-specific memory-access interconnect

H.264 Decoder: A Case Study in Multiple Design Points

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