High Level Test Generation / SW based Embedded Test

Abstract

As device geometries scale, product complexity has increased with more and more functionality embedded into integrated chips in recent times. In the processor domain, multiple cores with associated glue logic and cache all on a single die are becoming more and more popular. At the same time, product frequencies have gone up and the need to test for delay defects and marginal circuits is rising continually. This is exacerbated in recent times with the focus on lowpower design. While there has been a lot of progress in scan based delay test, the reliance on functional tests has continued. The biggest concern with scan test effectiveness is related to screening small delay defects. Gross delay defects can be tested using a good set of scan transition fault tests (scan AC tests). However questions remain with respect to the effectiveness of scan tests to screen small delay defects and also to test marginality related failures: for example, speed failures caused by issues like cross-capacitance, power droop etc. Functional tests are being used today for getting the last few DPM to reach quality goals. The reliance on functional tests is higher in products that push the process/design envelope to reach performance/power goals.The continued reliance on functional test for reaching quality goals is driving more efforts to be focused on high level test generation in recent times. As devices have evolved into SOC products with embedded cores, this has opened up new opportunities for core based functional test application. In the microprocessor domain, large caches have been integrated on the same die for some time now. The availability of large onchip cache has been taken advantage of to run functional tests that are stored in the cache. Additionally there have been recent efforts where we have employed the logic of the microprocessor to generate tests on the fly. Essentially we have been able to write intelligent software that resides in the chip, and during test application time, generates and applies interesting functional test sequences, thereby accomplishing a functional BIST technology.As SOC functionality increases, there is a big opportunity to configure the various modules in the die in such a way that the entire device can be tested in functional mode. Such corebased software tests can go a long way to enable at-speed functional test. Surprisingly what is needed to enable this is minimal DFT that configures the peripheral modules on the SOC in special DFT modes. Such a SW based functional test technology is essential when it comes to testing the interfaces between the various modules in SOCs. Even if core level testing is enabled with scan and other direct access test methods, inter-module interactions need functional content application to uncover delay defects and marginal circuit behavior in such interfaces.Finally the effectiveness of the scheme is measured by the fault coverage achieved by such functional tests. While methods to enable random tests to hit targeted module interactions can be devised easily, a...