High-per formance, highly reliable HfSiON gate dielectric for low Vth system LSI's

Abstract

Abstr actIn this paper, we demonstrate the improvement of HfSiON pFET characteristics with F incorporation technique, which might be a powerful tool to lower V th in pFET with both poly-Si and PC-FUSI gate. Using F implantation in channel region prior to HfSiON formation V th lowering up to~200mV is obtained without mobility degradation. Furthermore, impact of F incorporation in HfSiON is investigated from reliability aspect. V th stability during negative bias temperature stress is drastically improved which can be associated with F passivation of defects in HfSiON.