This article presents the design and implementation of a multi-stage radio-frequency (RF) passive polyphase filter (PPF). The layout parasitics and mismatch which deteriorate significantly the RF filter performance are analyzed and modeled. To reduce this parasitic degradation, a novel optimal layout technique is proposed. It is based on reproducing the same optimized PPF stage layout for the different stages while the desired bandwidth is ensured due to an optimal sizing of the inter-stages connections. This approach has been validated with on chip measurements. Using the proposed techniques more than 55 dB of image rejection over the [1.5; 3.3] GHz bandwidth is demonstrated while achieving zero power consumption and small silicon area in 130nm CMOS technology.