High‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2
            <i>
              <sup>m</sup>
            </i>
            )

Rashidi, Bahram; Farashahi, Reza Rezaeian; Sayedi, Sayed Masoud

doi:10.1049/iet-ifs.2015.0461

Cited by 30 publications

(25 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The comparison is based on parameters such as area consumption, CPD, number of clock cycles and computation time. In Table 5, works [14][15][16][17][18]20] are implemented based on ITA and work [10] is based on the EEA. Inversion architecture in the works [14][15][16][17] is constructed by one field multiplier, several multiplexers with m-bit inputs, squarer blocks (or exponentiation by power of 2 blocks), several m-bit registers and a control unit.…”

Section: Results and Comparisonmentioning

confidence: 99%

“…In recent years, different hardware implementations of the field inversion over F 2 m are presented in literature [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The works [2][3][4][5][6][7][8][9][10][11][12][13][14][15] are implemented in polynomial basis (PB). Several structures for the field inversion based on systolic architecture have been presented.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Efficient hardware structure for extended Euclidean‐based inversion over

Rashidi

2019

IET Computers & Digital Techniques

Self Cite

View full text Add to dashboard Cite

In this study, an efficient hardware structure for implementation of extended Euclidean algorithm (EEA) inversion based on a modified algorithm is presented. In the proposed algorithm, one iteration performs the operations corresponding to two iterations in previously reported EEA-based inversion algorithm. The proposed structure is implemented based on a modified algorithm with low path-delay and hardware consumption. The circuit performs one iteration of the algorithm in one clock cycle. Furthermore, to increase speed and reduce the latency of the structure, the authors applied the loop unrolling technique by replicating the body of the loop. Loop unrolling replaces a loop body by several copies of the body. The authors chose the number of copies based on the trade-off between hardware resources, critical path delay and the number of clock cycles. Therefore, the time and area parameters can be adjusted by different choices. The proposed architecture is simple, low cost and also the number of clock cycles in the structure are reduced compared to existing EEA-based works. The structure over two binary finite fields F 2 163 and F 2 233 has been successfully verified and implemented on Virtex-5 XC5VLX110 fieldprogrammable gate array. The comparison with other previous implementations of the inversion operation verifies that the proposed method has better improvement in terms of area × time complexity.

show abstract

Section: Results and Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient hardware structure for extended Euclidean‐based inversion over

Rashidi

2019

IET Computers & Digital Techniques

Self Cite

View full text Add to dashboard Cite

show abstract

“…In pursuit of low latency, 2 n units of combinational logic are used to speed up the calculation of powering at a large cost of area, which reaches the minimum theoretical clock cycles of one operation in [30]. A tree-structure-k-times squarer block is implemented in the ITA structure to achieve high clock frequency in [27].…”

Section: B Architecture Of Modular Inversionmentioning

confidence: 99%

Speed-Oriented Architecture for Binary Field Point Multiplication on Elliptic Curves

Zhong

Li³

et al. 2019

IEEE Access

View full text Add to dashboard Cite

This paper introduces a novel speed-oriented architecture of point multiplication in elliptic curve cryptography. A balanced full-precision multiplier is proposed to shorten latency, and a new modular inversion architecture is integrated to reduce the total number of clock cycles in point multiplication. A modified Montgomery Ladder algorithm that takes three clock cycles to calculate one input bit is proposed to best utilize hardware resources. A mixed-pipeline technique is used to balance the delay of different paths and increase frequency. The proposed architecture is implemented on GF(2 163) and GF(2 571), based on

show abstract

“…There are numerous algorithms that have been reported to implement PM, some of them are designed to reduce area and others to save the ECCP time. The main contribution of this work may be stated in the following points:  Implementing algorithms such as Montgomery [13][14][15][16][17], Itoh-Tsujii [12,15] and Karatsuba [18][19][20][21] for optimizing EC and finite field operations to improve speed, throughput, and/or computation time. The implementation is performed over GF2 163 and GF2 409  Optimizing area requirements by minimizing the Register File (RF) size in ECCP.…”

Section: Introductionmentioning

confidence: 99%

Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices

Khadra

Abdulrahman

Ismail

2020

Menoufia Journal of Electronic Engineering Research

View full text Add to dashboard Cite

An Elliptic Curve Crypto-Processor (ECCP) is a favorite public-key cryptosystem due to its small key size and its high security arithmetic unit. It is applied in constrained devices which often run on batteries and have limited processing, storage capabilities and low power. This research work presents an effective ECCP architecture for security in IoT and embedded devices. A finite field polynomial multiplier takes the most implementation effort of an ECCP because it is the most consuming operation for time and area. So, the objective is to implement the main operation of Point Multiplication (PM) = using FPGA. The aim is to obtain the optimal registers number for an area optimization of ECCP architecture. Moreover, it proposes a time optimization of ECCP based on the liveness analysis and exploiting forward paths. Also, a comparison between sequential and parallel hardware design of PM based on Montgomery ladder algorithm is provided. The developed ECCP design is implemented over Galois Fields GF (2 163) and GF (2 409) on Xilinx Integrated Synthesizes Environment (ISE) Virtex 6 FPGA. In case of GF (2 163), this work achieved an area saving that uses 2083 Flip Flops (FFs), 40876 Lookup Tables (LUTs) and 19824 occupied slices. The execution time is 1.963 s runs at a frequency of 369.529 MHz and consumes 5237.00 mW. In case of GF (2 409), this work achieved an area saving that uses 8129 Flip Flops (FFs), 42300 Lookup Tables (LUTs) and 18807 occupied slices. The execution time is 29 s runs at a frequency of 253.770 MHz and consumes 2 W. The obtained results are highly comparable with other state-of-the-art crypto-processor designs. The developed ECCP is applied as a case study of a cryptography protocol in ATMs.

show abstract

High‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2 ^m )

Cited by 30 publications

References 26 publications

Efficient hardware structure for extended Euclidean‐based inversion over

Efficient hardware structure for extended Euclidean‐based inversion over

Speed-Oriented Architecture for Binary Field Point Multiplication on Elliptic Curves

Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices

Contact Info

Product

Resources

About

High‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2 m )

Cited by 30 publications

References 26 publications

Efficient hardware structure for extended Euclidean‐based inversion over

Efficient hardware structure for extended Euclidean‐based inversion over

Speed-Oriented Architecture for Binary Field Point Multiplication on Elliptic Curves

Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices

Contact Info

Product

Resources

About

High‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2 ^m )