High-Performance Carry Select Adders

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

“…Most of the previous CaSeA designs such as basic architecture (BCSA), square root adder-based architecture (SQCSA), [2] (SQCSB), and [13] (SQCSC) improved the speed and area parameters, with more number of distinct elements in their designs. Existing SQRT CaSeAs has a variable length of inputs; they require variable sizes of the multiplexer which become more complicated in the physical design of ASIC.…”

“…The modified and improved version of the BE1 of SQCSB is proposed by SQCSC. The authors of [13] developed two new architectures based on 'carry enable' concept using an additional OR gate and 'Add-1 RCA' block. Both exhibit good performance by optimizing the logic to the maximum possible extent.…”

“…Two modified versions of Adders improved the speed, but the carry propagation through carry enables BE1 blocks is present which may be still minimized. An additional OR & AND gates along with complex XOR gates is still present in BE1 of SQCSC, and a 5-bit BE1 with input and output carry proposed by [13] is shown in figure 6. The final output carry is generated from the last stage OR gate, depending on the previous gating circuit.…”

“…For the construction of novel memory type adders, traditional CMOS circuits are combined with magnetic memories and achieved a markable improvement compared to previous memory type adders [12]. Improvement in speed, area, power dissipation, PDP, and ADP is achieved in every modified version of SQRT adders compared to conventional SQRT adders [13]. Multiplexers are used in a few self-checking CaSeAs resulting in an improvement in the area about 20%.…”