High-Performance IIR Filter Implementation Using FPGA

Vijay, Vallabhuni; Rao, V. R. Seshagiri; Chaitanya, Kancharapu; Venkateshwarlu, S. China; Pittala, Chandra Shaker; Vallabhuni, Rajeev Ratna

doi:10.1109/icrtcst54752.2022.9781944

Cited by 15 publications

(16 citation statements)

References 6 publications

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“…Due to their higher threshold voltage, previously known methods cannot be operated at low voltages. [32][33][34][35][36][37][38][39] This tells us that the previously known and current known methodologies had a significant drawback which creates the need to invent new methodologies to make the circuit more efficient. It is also known that the static leakage current is also more in existing and previously known methodologies.…”

Section: Significant Drawbacks In the Existed Methodsmentioning

confidence: 99%

ADC: Novel Methodology for Code Converter Application for Data Processing

2023

VLSI

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An innovative "Multiplexer based Thermometer to Binary code encoder" is presented in this paper. This paper shows a relative decrease in the total count of multiplexers used which eventually reduces the no of transistors used when compared to traditional Architectures. The requirement for further more inverters is also eliminated in the proposed model. The input thermometer code is at first is converted to the respective gray code with the help of 2:1 multiplexer. Thereafter, using two-input XOR gates the conversion process of gray code to respective binary codes takes place. Outcomes of simulation reveal that there is an approximately 80% decrease in the power consumption which is a great reduction actually when differentiated with previously known and current encoder architectures with the delay being reduced from 0.472ps to 0.366 ps. This throws a light on modern power-saving encoder architectures and has a greater significance in the future. The proposed encoder gives a better application for future generation advanced ADC & related circuits.

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Section: Significant Drawbacks In the Existed Methodsmentioning

confidence: 99%

ADC: Novel Methodology for Code Converter Application for Data Processing

2023

VLSI

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“…The method minimizes the weighted least square cost function using the BFGS method and the results demonstrate the effectiveness of this approach in achieving excellent filter design outcomes. The work by Vijay, et al (2022) proposes an IIR filter model referred to as parallel pipeline, which is built upon a FIR filter including the two-level pipeline-based IIR filter and a look-ahead-based models, both of which have been reported to yield substantial enhancements in filter efficiency.…”

Section: Introductionmentioning

confidence: 99%

An Innovative Embedded Processor-Based Signal Phase Shifter Algorithm

Hamza,

Hussein

2024

ARO

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Digital filtration is widely used today in many application fields, and with the increased use of low-cost embedded processors, it can be applied to vast areas. A drawback of digital filtration algorithms is the introduction of phase angle shifts in the filtered signals, thereby creating undesirable characteristics in many application fields. In this work, low-pass filters of finite impulse response and infinite impulse response types are designed with an innovative buffering scheme to delay a digitally low-passed signal by an angle ranging from 0° to 180° for real-time signals. The application of the filtration and buffering scheme on a cost-effective embedded processor with limited signal processing capabilities opens the horizons for its applicability in many signal processing fields. In assessing its practicality, the generated filtered output signal is correlated with the original signal (a low-passed version), revealing correlation values reaching 0.99 in certain instances. The novelty of the proposed approach enables its application to a broad-spectrum area of digital signal filtration.

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“…Because of stability concerns, the twin port designs that implement read disturb-free feature like that seen within the 7T and 8T cell implementation might become more practical in the futures RAM cell implementation. [1][2][3][4][5] Zone scaling abilities of numerous types of SRAM, edge help answers for voltage changeability issues, which depend on different endeavors from 6T to 8T and 10T, yet additionally fuse of various voltage supply for cell terminal biasing and having arrangement controls of read and write activity was thought about, the varieties in SRAM arrangements were investigated considering an effect on the necessary territory overhead for each plan arrangement given by ever-expanding irregular varieties. Unlike the DRAM cell, total power consumption, static power dissipation, dynamic power dissipation, static current and area which will affect the speed of operation of novel SRAM cell.…”

Section: Introductionmentioning

confidence: 99%

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

2023

VLSI

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In the ultra-low-power implementation, center circuits of numerous frameworks are activated by inadequate occasions, for example, the Internet of Things (IoT) sensors and implantable clinical consideration. To guarantee that, the sensors get each and every occasion showing up whenever the circuits operate in standby mode the most of the time. Under such conditions, static power dominates in the total power consumption. For these implementations, the lessening framework leakage current can straightforwardly accomplish the greatest effectiveness of the complete framework power utilization. Since the SRAM cluster takes up a bigger bit of the circuit, it is important to decrease the power utilization of the SRAM exhibit so as to lessen circuit all-out power. Band-to-band tunneling (BTBT) mechanism introduced silicon tunnel FET (TFET), MOSFET compatible fabrication process and ultra-steep SS, which can break the 60mV/dec limitation of MOSFET at room temperature and ultralow off-state current. Subsequently, it is required to be a promising contender for an ultra-low-power rationale circuit. The impact of forward p-I-n leakage current could prompt harm to the static noise margin (SNM), static power and power defer result of the SRAM circuit. So the proposed topology can stay away from the p-I-n intersection, by expanding SRAM cell read and hold static noise margin (SNM) and diminishing static power utilization drastically.

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High-Performance IIR Filter Implementation Using FPGA

Cited by 15 publications

References 6 publications

ADC: Novel Methodology for Code Converter Application for Data Processing

ADC: Novel Methodology for Code Converter Application for Data Processing

An Innovative Embedded Processor-Based Signal Phase Shifter Algorithm

Flip-Flop Realization: Conventional Memory Elements Design with Transistor Nodes

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