High quality nanocrystalline silicon thin film fabricated by inductively coupled plasma chemical vapor deposition at 350°C

Han, Shuai; Kim, Sun–Jae; Park, Joong−Hyun; Choi, Sung-Hwan; Han, Min−Koo

doi:10.1016/j.jnoncrysol.2007.09.082

Cited by 12 publications

(6 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The flow rate of Helium : Silane (SiH 4 ) was 40:3 [sccm]. [9] The base pressure in the reactor was less than 1 mT and the process pressure during the deposition was set to 50mT and the ICP power was 700W.…”

Section: Experimental and Resultsmentioning

confidence: 99%

Highly Stable Bottom-Gate Nanocrystalline Silicon Thin Film Transistor Fabricated Employing ICP-CVD

Kim

Han

Kwon³

et al. 2008

ECS Trans.

Self Cite

View full text Add to dashboard Cite

Bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) were fabricated and evaluated their characteristics and electrical stability under various stress condition. nc-Si with high crystallinity was deposited employing Inductively coupled plasma chemical vapor deposition(ICP-CVD) system. We employed helium gas diluted deposition and all the process temperature was kept under 350 o C. We fabricated conventional inverted-staggered nc-Si TFTs. Fabricated nc-Si TFTs showed fine electrical characteristics, such as electrical mobility of 0.64~0.77 cm 2 /V·sec. We investigated its stability through constant-voltage stress and constant-current stress. The threshold voltage shift after 30,000 seconds gate bias (10V) stress was only 0.098V, which is considerably less compared to a-Si:H TFT. Under the static current stress condition, the threshold voltage of the nc-Si TFT was shifted less than that of a-Si:H TFT. It demonstrates that nc-Si TFT exhibit better stability than conventional a-Si:H TFT.

show abstract

Section: Experimental and Resultsmentioning

confidence: 99%

Highly Stable Bottom-Gate Nanocrystalline Silicon Thin Film Transistor Fabricated Employing ICP-CVD

Kim

Han

Kwon³

et al. 2008

ECS Trans.

Self Cite

View full text Add to dashboard Cite

show abstract

“…Vertically aligned crystalline growth occurred on the SiN X gate insulator, which suggests that a thin incubation layer was formed during nc-Si deposition. 25) Figure 3 shows the transfer characteristics of the nc-Si TFT. The field effect mobility (FE) at a V DS of 0.1 V, the threshold voltage (V TH ), the subthreshold slope, and the on/off ratio were 0.77 cm 2 /(VÁs), 3.69 V, 1.66 V/dec, and !1 Â 10 6 , respectively.…”

Section: Bottom Gate Nc-si Tftmentioning

confidence: 99%

Effect of Drain Bias Stress on Stability of Nanocrystalline Silicon Thin Film Transistors with Various Channel Lengths

Kim

Park

et al. 2010

Jpn. J. Appl. Phys.

Self Cite

View full text Add to dashboard Cite

In this study, we demonstrate the thermal-stable characteristics of a metamorphic double -doped heterostructure field-effect transistor (MDDFET). The variations in drain current density and extrinsic transconductance of the studied device are as low as +0.3 and À2:5% from 300 to 420 K. When the temperature increases from 360 to 380 K, positive changes of transconductance and drain current are observed, which is different from that observed in most FETs. The thermal-stable characteristics can be attributed to the coupled wave function, inducing a larger carrier distribution in the undoped high-speed In 0:6 Ga 0:6 As region of the In 0:5 Ga 0:5 As/ þ /In 0:5 Ga 0:5 As/In 0:6 Ga 0:4 As/In 0:5 Ga 0:5 As/ þ /In 0:5 Ga 0:5 As channel when temperature increases.

show abstract

“…However, nc-Si films deposited at this temperature have an amorphous incubation layer at the interface with the substrate (2). This phenomenon was known to deteriorate the performance of the transistors because bottom-gate TFTs channel is formed in the lower part of active layers (3). In order to reduce the incubation layer thickness of the nc-Si films prepared at low temperatures, we attempted graded profiling of the hydrogen dilution ratio and pressure in the Cat-CVD.…”

Section: Introductionmentioning

confidence: 99%

Characteristiscs of Nanocrystalline Silicon Films Deposited by Cat-CVD below 100 °C

Song¹,

Hong²

2013

ECS Trans.

View full text Add to dashboard Cite

Nanocrystalline Silicon (nc-Si) films were deposited by catalytic chemical vapor deposition (Cat-CVD) at a low substrate temperature (100 °C) for use as an active layer in bottom-gate thin-film transistors (TFTs). Hydrogen dilution technique was attempted to increase the crystalline volume fraction (Xc). The hydrogen dilution ratio, RH = [H2]/[SiH4], was varied from 44 to 74. In order to obtain nc-Si film with a high XC, a thin incubation layer and a fast deposition rate simultaneously, we varied RH and pressure as the deposition proceeded. When the pressure was set to 50 mTorr during the initial stage and changed to 60 mTorr for the rest of the deposition, the incubation layer thickness was suppressed to 4 nm.

show abstract

High quality nanocrystalline silicon thin film fabricated by inductively coupled plasma chemical vapor deposition at 350°C

Cited by 12 publications

References 18 publications

Highly Stable Bottom-Gate Nanocrystalline Silicon Thin Film Transistor Fabricated Employing ICP-CVD

Highly Stable Bottom-Gate Nanocrystalline Silicon Thin Film Transistor Fabricated Employing ICP-CVD

Effect of Drain Bias Stress on Stability of Nanocrystalline Silicon Thin Film Transistors with Various Channel Lengths

Characteristiscs of Nanocrystalline Silicon Films Deposited by Cat-CVD below 100 °C

Contact Info

Product

Resources

About