High Resolution Single-Chip Radix II FFT Processor for High- Tech Application

Abstract

Electrical motors are vital components of many industrial processes and their operation failure leads losing in production line. Motor functionality and its behavior should be monitored to avoid production failure catastrophe. Hence, a high-tech DSP processor is a significant method for electrical harmonic analysis that can be realized as embedded systems. This chapter introduces principal embedded design of novel high-tech 1024-point FFT processor architecture for high performance harmonic measurement techniques. In FFT processor algorithm pipelining and parallel implementation are incorporated in order to enhance the performance. The proposed FFT makes use of floating point to realize higher precision FFT. Since floating-point architecture limits the maximum clock frequency and increases the power consumption, the chapter focuses on improving the speed, area, resolution and power consumption, as well as latency for the FFT. It illustrates very large-scale integration (VLSI) implementation of the floating-point parallel pipelined (FPP) 1024-point Radix II FFT processor with applying novel architecture that makes use of only single butterfly incorporation of intelligent controller. The functionality of the conventional Radix II FFT was verified as embedded in FPGA prototyping. For area and power consumption, the proposed Radix II FPP-FFT was optimized in ASIC under Silterra 0.18 µm and Mimos 0.35 µm technology libraries.

Exploring the CORDIC Algorithm and Clock-Gating for Power-Efficient Fast Fourier Transform Hardware Architectures

“…These twiddle factors are half the number of FFT points, and based on the stage used, the number of coefficients required also varies. The proposed architecture was synthesized in CMOS 0.18 um, and works with 36 bits input size, at 100 MHz, and consumes 39 mW, at a supply voltage of 1.8 V. An embedded design of a 1024-point FFT processor architecture for high-performance harmonic measurement techniques are proposed in [18]. The FFT processor algorithm incorporates both pipelining and parallel strategies to enhance performance.…”