High-Speed and Low-Power Recursive Rounding Based Approximate Multipliers for Error-Resilience Applications

Abstract

Approximate multipliers play a requisite role in error-resilience applications having a trade-off between error and design metrics. Consequently, in this paper, recursive rounding-based approximate multipliers are proposed to enhance both error and design metrics. First, in the n/2-bit, the most significant and least significant bits are chosen for every n-bit input operand. Next, these n/2-bits are rounded to the closest power of two in the proposed multipliers architecture. Succeedingly, the final multiplication product is achieved using rounding, shifters, and adders. On top of that, all the proposed and existing multipliers are developed using Verilog Code with inputs widths ranging from 8-bit to 32-bit, synthesized using Cadence RTL compiler, and simulated using Vivado and MATLAB for Image Smoothing Filter. Further, the error and design metrics of the newly developed and existing multipliers are analyzed. It is observed through the simulation results that reductions in delay and power consumption are achieved through the proposed multipliers on an average of 21.35% and 40%, respectively, compared to that of state-of-the-art multipliers. Furthermore, the proposed multipliers also provide high PSNR and SSIM over the existing multipliers after incorporating the proposed multipliers in the image smoothing filter, which is suitable for Error-Resilience applications.