High speed / low power architectures for the finite radon transform

Chandrasekaran, S.; Amira, Abbes

doi:10.1109/fpl.2005.1515763

Cited by 10 publications

(23 citation statements)

References 4 publications

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“…In [11] two power efficient architectures for the FRAT with time complexities O(p 2 (p + 1)) and O(p 2 ), respectively have been proposed. The first architecture is a ''Serial Architecture'' based on the FRAT pseudocode and optimised for FPGA implementation.…”

Section: Related Workmentioning

confidence: 99%

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

Chandrasekaran

Amira

Shi

et al. 2008

J Real-Time Image Proc

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In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p 2 ), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.

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Section: Related Workmentioning

confidence: 99%

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

Chandrasekaran

Amira

Shi

et al. 2008

J Real-Time Image Proc

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“…In addition to the summary of existing FRAT implementation on FPGA that have been discussed [71][72][73], [75], [76], Table 2.4 lists the important issues, such as the FPGA devices involved, programming approaches as well as the target applications. Virtex-E Handel-C and CoreGen Image processing [72] Virtex-II Handel-C Image processing [73] Virtex-E N/S Image processing [75] Virtex-II Verilog Image processing [76] Virtex-E Handel-C Image processing Note: N/S: Not stated…”

Section: Reconfigurable Architectures 46mentioning

confidence: 99%

“…Virtex-E Handel-C and CoreGen Image processing [72] Virtex-II Handel-C Image processing [73] Virtex-E N/S Image processing [75] Virtex-II Verilog Image processing [76] Virtex-E Handel-C Image processing Note: N/S: Not stated…”

Section: Reconfigurable Architectures 46mentioning

confidence: 99%

“…In terms of programming approaches, Handel-C is used in [71], [72] and [76], whilst the target FPGA devices change inline with the FPGA technology advancement. Figure 2.14: Review of FRAT's FPGA-based implementation.…”

Section: Reconfigurable Architectures 46mentioning

confidence: 99%

“…To overcome these restrictions, hardware implementation of FRAT is an interesting domain of study, especially for medical imaging application. Existing limited hardware implementation of the FRAT [71][72][73], [75], [76] in medical imaging application opens a huge gap to be filled. Finally, summary is given in Section 4.5.…”

Section: Overview 85mentioning

confidence: 99%

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Efficient reconfigurable architectures for 3D medical image compression

Ahmad

Amira

2009

2009 International Conference on Field-Programmable Technology

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A AbstractRecently, the more widespread use of three-dimensional (3-D) imaging modalities, such as magnetic resonance imaging (MRI), computed tomography (CT), positron emission tomography (PET), and ultrasound (US) have generated a massive amount of volumetric data. These have provided an impetus to the development of other applications, in particular telemedicine and teleradiology. In these fields, medical image compression is important since both efficient storage and transmission of data In summary, this research is tackling the issues of massive 3-D medical volumes data that requires compression as well as hardware implementation to accelerate the slowest operations in the system. Results obtained also reveal a significant achievement in terms of the architecture efficiency and applications performance.

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Real-time hardware acceleration of the trace transform

Fahmy

Bouganis

Cheung

et al. 2007

J Real-Time Image Proc

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The trace transform is a novel algorithm that has been shown to be effective in a number of image recognition tasks. It is a generalisation of the Radon transform that has been widely used in image processing for decades. Its generality-allowing multiple functions to be used in the mapping-leads to an algorithm that can be tailored to specific applications. However, its computation complexity has been a barrier to its widespread adoption. By harnessing the heterogeneous resources on a modern FPGA, the algorithm is significantly accelerated. Here, a flexible system is developed that allows for a wide array of functionals to be computed without re-implementing the design. The system is fully scalable, such that the number and complexity of functionals does not affect the speed of the circuit. The heterogeneous resources of the FPGA platform are then used to develop a set of flexible functional blocks that can each implement a number of different mathematical functionals. The combined result of this design is a system that can compute the trace transform on a 256 9 256 pixel image at 26 fps, enabling real-time processing of captured video frames.

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High speed / low power architectures for the finite radon transform

Cited by 10 publications

References 4 publications

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

Efficient reconfigurable architectures for 3D medical image compression

Real-time hardware acceleration of the trace transform

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