2019
DOI: 10.1109/tcsvt.2018.2826074
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Highly Paralleled Low-Cost Embedded HEVC Video Encoder on TI KeyStone Multicore DSP

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Cited by 6 publications
(5 citation statements)
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References 39 publications
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“…Jiang et al [64] proposed a SIMD-accelerated HEVC encoder implemented on a digital signal processor (DSP). The authors focused on improving data parallelism and minimizing the memory traic overhead.…”
Section: Inter-frame Compressionmentioning
confidence: 99%
“…Jiang et al [64] proposed a SIMD-accelerated HEVC encoder implemented on a digital signal processor (DSP). The authors focused on improving data parallelism and minimizing the memory traic overhead.…”
Section: Inter-frame Compressionmentioning
confidence: 99%
“…In [126], Sun introduced a Markov Chain model based data pre-fetching algorithm to speed up ME on multi-core DSPs through improving efficiency of data access. In our recent work [127], a multi-core DSP-based highly-paralleled HEVC encoder solution was implemented. The overall structure of HEVC encoder was re-designed to well support the encoding parallelism and lowdelay low-memory multicore data transmission mechanism was designed to reduce data access latency Besides, SIMD-based optimizations are also integrated.…”
Section: Dsp-based Implementationmentioning
confidence: 99%
“…Block partitioning structure is regards as core infrastructure based on which sophisticated coding tools are supported [127].…”
Section: A Quadtree Plus Binary Tree (Qtbt) Block Partitioningmentioning
confidence: 99%
See 1 more Smart Citation
“…In total, 3 compression levels and 3 kinds of projection are considered, and thus 9 different impaired sequences correspond to each reference sequence. Specifically, we use H.265 [12,18], a state-of-the-art video compression standard, to compress the reference sequences. For each sequence, three test points are obtained with quantization parameter (QP) = 27, 37 and 42 [52].…”
Section: Omnidirectional Sequencesmentioning
confidence: 99%