2019
DOI: 10.1016/j.orgel.2019.105391
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Highly stable flexible organic field-effect transistors with Parylene-C gate dielectrics on a flexible substrate

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Cited by 22 publications
(14 citation statements)
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“…In the third chamber, the monomer gas was deposited and self-assembled to form the Parylene-C on top of the Si/SiO2/IGZO substrate at 10E-6 mBar vacuum level. The CVD deposition of parylene-c is the best choice for the conformal coatings 37 , insulation and pinhole-free surface 38 .…”
Section: Methodsmentioning
confidence: 99%
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“…In the third chamber, the monomer gas was deposited and self-assembled to form the Parylene-C on top of the Si/SiO2/IGZO substrate at 10E-6 mBar vacuum level. The CVD deposition of parylene-c is the best choice for the conformal coatings 37 , insulation and pinhole-free surface 38 .…”
Section: Methodsmentioning
confidence: 99%
“…In the third chamber, the monomer gas was deposited and self-assembled to form the Parylene-C on top of the Si/SiO 2 /IGZO substrate at the 10 × 10 –6 mBar vacuum level. The CVD of Parylene-c is the best choice for the conformal coatings, insulation, and pinhole-free surfaces . In this case, the sample is not exposed to higher temperatures and there is no physical damage to the thin-film.…”
Section: Experimental Sectionmentioning
confidence: 99%
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“…PPx coatings are widely used as passivation layers. Due to these properties, PPx is a promising candidate for polymeric gate dielectric layers. However, most previous studies on PPx films as dielectric layers (not passivation layers) have focused on organic semiconductors, and only a limited number of studies on metal oxide semiconductors have been reported. Additionally, there has been significant progress in the preparation and application of functionalizable PPx coatings over the past two decades. Conformal and pinhole-free polymeric thin films have been prepared using the Gorham method with both commercially available and newly synthesized precursors (i.e., monomeric [2.2]­paracyclophanes), meaning that one can design different types of dielectric layers using a single method.…”
Section: Introductionmentioning
confidence: 99%
“…Due to the increasing development of electronic equipment and being the incessant scaling down of device sizes, semiconductor devices are very close to their physical limits, there is an instantaneous need to develop next-generation technologies, in the designation of both device architecture and physics [1][2]. With the technology of getting smaller which confronts Moore's law i.e., the transistor poll on a chip multiplies at the rate of 2X per every 2 years [3], so nano electronic researchers are greatly keen on studying distinctive nanodevices like carbon nanotube/graphene tunnel field-effect transistors (FETs) and sensors [4][5][6][7][8], organic FETs [9][10], single-molecule devices [11][12], single-electron transistors (SETs) [13][14] and junction-less nanowire transistors [15][16].…”
Section: Introductionmentioning
confidence: 99%