How Many Test Vectors We Need to Detect a Bridging Fault?

Abstract

The growing dispersion of ICs’ parameters poses relevant uncertainties on gate output conductances and logic thresholds which play a main role in bridging fault detection. In this evolving context, the quality of fault simulation and test generation tools making use of nominal parameters should be verified. To analyze this problem we have studied bridging fault detection in combinational ICs in the presence of growing variations of IC’s parameters. Results show that a single test is not sufficient to ensure acceptable escape probabilities. Conversely, the minimal number of test vectors required to provide a null escape probability is upper bounded with respect to variations in the standard deviation of IC’s parameters. This result has been verified by means of Monte Carlo electrical level simulation. We propose a method to derive these minimal test sets in the case of low frequency tests. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability. These tools have been applied to a set of combinational benchmarks

Input Bridging Fault and Non Feedback Bridging Fault Detection and Test Vector Generation by Boolean Satisfiability Method

“…Boolean satisfiability method is sorted into 3 steps - Getting fault free or good circuit equations  Getting faulty circuit  Activation of propagation path These steps play an important role in detection and this method requires the conjunctive normal form equation [5]. For example for NAND gate CNF (conjunctive normal form) is written as follows:…”

Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults

“…As for non-feedback bridging faults, several front-and back-gate input configurations may excite the fault. As an alternative to accurate models [3], conservative approaches can be used (such as the one described in [14] for nonfeedback bridging faults), trying to compute a set of test vectors ensuring the detection of a non-feedback bridging fault independently of circuit parameters variations. Such approaches can be extended to FBFs.…”

“…Of course, this assumption may not hold, but it is conservative because of the relevant variations of circuit parameters in nano-CMOS ICs [24]. These variations, in fact, make the outcome of conductance conflicts as unpredictable (see [14] for a discussion in the case of non-FBFs), thus requiring to account also for oscillations. 1 Conversely, if accurate results are required, the electricallevel details of the gates involved in the feedback loop should be accounted for.…”

“…These reasons motivated the development of ATPG strategies targeting the detection of oscillating FBFs and easily extendable to other faults that shows an oscillating behavior. To this purpose, we exploit Boolean satisfiabilitybased (SAT) test-generation techniques [11] that have been shown to be capable of handling large circuits [12] for a wide variety of fault models including: 1) stuck-at faults [11], [12], [13]; 2) bridging faults [8], [14]; 3) open faults [10]; 4) delay faults [15], [16].…”