2019
DOI: 10.1109/jstqe.2019.2904445
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Hybrid III–V/Silicon Technology for Laser Integration on a 200-mm Fully CMOS-Compatible Silicon Photonics Platform

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Cited by 58 publications
(35 citation statements)
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“…The structure was then bonded to a 200 mm silicon wafer on which a 200 nm‐thick thermal silica layer was formed prior to the bonding. This bonding process is done at CEA‐LETI's 200 mm line . In our approach, the oxidized Si substrate is a relevant test structure to simulate the bonding interface behavior of an SOI substrate under epitaxial growth conditions.…”
Section: Fabrication Processmentioning
confidence: 99%
“…The structure was then bonded to a 200 mm silicon wafer on which a 200 nm‐thick thermal silica layer was formed prior to the bonding. This bonding process is done at CEA‐LETI's 200 mm line . In our approach, the oxidized Si substrate is a relevant test structure to simulate the bonding interface behavior of an SOI substrate under epitaxial growth conditions.…”
Section: Fabrication Processmentioning
confidence: 99%
“…In this case, the process steps following the die bonding must be done using CMOS foundry compatible process and material. Such integration has been demonstrated [147] on 200 mm wafer using localized waveguide thickening and CMOS compatible contact [148] and process, as demonstrated.…”
Section: Place Of Iii-v Materials On Si Photonics Circuitsmentioning
confidence: 97%
“…Demonstrations of III-V integration with advanced SiPh platforms have been reported. 276,277 Demonstrations of epitaxial growth of III-V on Si have also been reported despite the large lattice mismatch between Si and III-V (for example, InP has 8% lattice mismatch with Si). 278,279 The integration of III-V on silicon also provides a route for the implementation of efficient high-speed modulators because they provide (a) a large electron-induced refractive-index change, (b) a high electron mobility, and (c) a low carrier-plasma absorption.…”
Section: Iii-v Semiconductorsmentioning
confidence: 99%