Hybrid predication model for instruction level parallelism

Abstract

This paper presents a hybrid predication model in analogy to the delayed branching technique with overlapped delayed slots by integrating two different predication models. Predicated-execution is considered a promising branch handling technique. A few models have been proposed for predicated-execution, the most known model has succeeded to provide ILP processors with enough parallel instructions for efficient resources utilization. Unfortunately, false parallelism is introduced by the instructions provided from the nullified paths (large dynamic code expansion). Another predicatedexecution model has managed to decrease the dynamic code expansion, with the cost of limiting the parallelism exploited and increasing the static code expansion. The presented hybrid predication model managed to integrate the advantages of the two models by decreasing the code expansion both dynamically and statically, especially for conditional code structures included within loops. The various conducted experiments aimed to provide an evaluation for the proposed model via simulator. The results proved that the presented hybrid predication model can achieve better utilization of register and shorter schedules with the same issue-width compared with the other existing models.