Hybrid SPM-cache architectures to achieve high time predictability and performance

Zhang, Wei; Ding, Yiqiang

doi:10.1109/asap.2013.6567593

Cited by 13 publications

(2 citation statements)

References 25 publications

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“…Kang et al [23] introduced a synergetic memory allocation method to exploit SPM to reduce data cache pollution. Zhang et al [24] studied hybrid on-chip memory architecture that can leverage the SPM to achieve time predictability while exploiting the cache to improve the average-case performance. In the past, Panda et al [25] investigated partitioning scalar and array variables into SPM and data cache to minimize the execution time for embedded applications.…”

Section: Related Workmentioning

confidence: 99%

Reducing cache leakage energy for hybrid SPM-cache architectures

Wen

Zhang

2014

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

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In this paper, we study how to reduce the cache leakage energy efficiently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. Since SPM can reduce the access frequency to the cache, we find it is possible to place the cache lines of the hybrid SPMcache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without significant performance degradation. Also, we propose a Hybrid Drowsy-Gated Vdd (HDG) technique, which can adaptively exploit both short and long idle intervals to minimize leakage energy with insignificant performance overhead.

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Section: Related Workmentioning

confidence: 99%

Reducing cache leakage energy for hybrid SPM-cache architectures

Wen

Zhang

2014

Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

Self Cite

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“…T-CREST [49], MERASA [54] and parMERASA [53] projects also have investigated time-predictability focused core architecture, cache, cache coherence protocol, system-bus, and DRAM controller designs [50,24,48,22,43,44,34,35]. There are also many other proposals, which focus on improving timing predictability of each individual shared hardware component-such as time predictable shared caches [61,62,33], hybrid SPM-cache architecture [65], and predictable DRAM controllers [60,18,30,15]. In most proposals, the basic approach has been to provide space and time partitioning of hardware resources to each critical real-time task or the cores that are designated to execute such tasks.…”

Section: Related Workmentioning

confidence: 99%

Deterministic Memory Abstraction and Supporting Multicore System Architecture

Farshchi,

Valsan,

Mancuso

et al. 2017

Preprint

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Poor time predictability of multicore processors has been a long-standing challenge in the real-time systems community. In this paper, we make a case that a fundamental problem that prevents efficient and predictable real-time computing on multicore is the lack of a proper memory abstraction to express memory criticality, which cuts across various layers of the system: the application, OS, and hardware. We, therefore, propose a new holistic resource management approach driven by a new memory abstraction, which we call Deterministic Memory. The key characteristic of deterministic memory is that the platform-the OS and hardware-guarantees small and tightly bounded worst-case memory access timing. In contrast, we call the conventional memory abstraction as best-effort memory in which only highly pessimistic worst-case bounds can be achieved. We propose to utilize both abstractions to achieve high time predictability but without significantly sacrificing performance. We present deterministic memory-aware OS and architecture designs, including OS-level page allocator, hardware-level cache, and DRAM controller designs. We implement the proposed OS and architecture extensions on Linux and gem5 simulator. Our evaluation results, using a set of synthetic and real-world benchmarks, demonstrate the feasibility and effectiveness of our approach.

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Optimization

Marwedel¹

2021

Embedded Systems

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Embedded systems have to be efficient (at least) with respect to the objectives considered in this book. In particular, this applies to resource-constrained mobile systems, including sensor networks embedded in the Internet of Things. In order to achieve this goal, many optimizations have been developed. Only a small subset of those can be mentioned in this book. In this chapter, we will present a selected set of such optimizations. This chapter is structured as follows: first of all, we will present some high-level optimization techniques, which could precede compilation of source code or could be integrated into it. We will then describe concurrency management for tasks. Section 7.3 comprises advanced compilation techniques. The final Sect. 7.4 introduces power and thermal management techniques.

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Hybrid SPM-cache architectures to achieve high time predictability and performance

Cited by 13 publications

References 25 publications

Reducing cache leakage energy for hybrid SPM-cache architectures

Reducing cache leakage energy for hybrid SPM-cache architectures

Deterministic Memory Abstraction and Supporting Multicore System Architecture

Optimization

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