<i>cecApprox:</i> Enabling Automated Combinational Equivalence Checking for Approximate Circuits

Jha, Chandan Kumar; Hassan, Muhammad; Drechsler, Rolf

doi:10.1109/tcsi.2024.3388256

IEEE Trans. Circuits Syst. I

2024

DOI: 10.1109/tcsi.2024.3388256

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cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits

Chandan Kumar Jha,

Muhammad Hassan,

Rolf Drechsler

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2024

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Cited by 1 publication

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EnR: extend and reduce methodology to enable formal verification of truncated adders

Jha,

Qayyum,

Hassan

et al. 2024

It - Information Technology

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Truncated adders are widely used in applications where using lower bit-width is enough to generate the desired outputs. Truncated adders give benefits in area, power, and delay as compared to their non-truncated counterparts. While prior works deal with the formal verification of n-bit adders, there is no prior work dealing with the formal verification of unverified m-bit truncated adders using verified n-bit adder designs, where m < ${< } $ n. In this work, we propose a methodology that enables the verification for any truncated adder designs, irrespective of the architecture, called Extend and Reduce (EnR). EnR uses a three-step methodology to formally verify the truncated adders, which are considered as Design Under Verification (DUV). Firstly, it extends the bit-width of the DUV (truncated adder) to match with the nearest higher 2 n -bit adder, called an Extended Truncated Adder (ETA). Secondly, it reduces off-the-shelf formally verified golden reference adder design by forcing 0’s at the input bits to match it to the extended DUV design and re-synthesizing it to generate a Reduced Golden Adder (RGA). Lastly, a combinational equivalence check is then performed between the ETA and the RGA for formal verification. If the truncated adder is correct, the ETA and RGA are equivalent and vice versa. We evaluate a number and variety of adder designs to show the efficacy of the EnR methodology. We performed the formal verification using Binary Decision Diagrams (BDDs) and And-Inverter Graphs (AIGs). Lastly, we show the scalability of EnR methodology using adders up to a bit-width of 512 bits. ACM CCS Hardware → Arithmetic and datapath circuits; Combinational circuits; Equivalence checking; Functional verification; Electronic design automation.

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EnR: extend and reduce methodology to enable formal verification of truncated adders

Jha,

Qayyum,

Hassan

et al. 2024

It - Information Technology

View full text Add to dashboard Cite

show abstract

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cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits

Cited by 1 publication

References 44 publications

EnR: extend and reduce methodology to enable formal verification of truncated adders

EnR: extend and reduce methodology to enable formal verification of truncated adders

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