IBIS-AMI Based PAM4 Signaling and FEC Technique for 25 Gb/s Serial Link

Abstract

This paper investigates Input/Output Buffer Information Specification Algorithmic Model Interface (IBIS-AMI) model extension for 25Gb/s PAM4 (4-level Pulse Amplitude Modulation) serial link to improve the development efficiency. By using the ADS (Advanced Design System) Channel Simulator, the effects of device package, jitter and crosstalk on the actual performance are studied at first. Then, for forward error correction (FEC) technique, the bit error rate (BER) performance and the bathtub curves are analyzed in detail. Simulation results show that device package, jitter and crosstalk can make the link performance worse. And much better performance can be obtained by using the combination of equalization and FEC techniques compared with using the equalization technique separately.

A COM Based High Speed Serial Link Optimization Using Machine Learning

“…To improve signal quality in high-speed wireline communication, various optimization methods have been explored not only in the system development, but also in transceiver design. Among them, IBIS-AMI (Input/output Buffer Information Specification-Algorithm Model Interface) [1], which models input/output behavior as well as algorithm for end-to-end high-speed serial link, has become an effective method, attracting much interests since it is proposed. This method, however, requires a large number of bits in simulation to optimize parameters, resulting in a long simulation time.…”