iBoX &amp;#x2014; Jitter based Power Supply Noise sensor

Valka, M.; Bosio, Alberto; Dilillo, Luigi; Todri, A.; Virazel, Arnaud; Girard, Patrick; Debaud, Philippe; Guilhot, S.

doi:10.1109/ets.2014.6847830

Cited by 2 publications

(2 citation statements)

References 4 publications

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“…9. In this paper we selected the over-sampling technique presented in [11]. Since our goal is to measure the noise of the running application by indirectly measure the jitter, the over-sampling technique fits well our needs.…”

Section: ) Jitter Estimatormentioning

confidence: 95%

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Auto-adaptive ultra-low power IC

Bosio

Debaud

Girard

et al. 2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

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International audienceApproximate computing has been adopted as a promising approach to energy-efficient design of digital systems. Actually the straightforward idea is to lower the supplied voltage level until errors appear. These errors can be "implicitly" tolerated since the application accepts some loss of quality or optimality in the computed result(s). This paper aims at targeting applications that cannot accept loss of quality. We propose an architecture able to auto-adapts the supplied voltage level in order to fit the actual running application. The key concept is a preliminary characterization phase that exploits the benefit of approximate computing

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Section: ) Jitter Estimatormentioning

confidence: 95%

“…Actually two techniques are used to measure the jitter affecting a signal: (i) under-sampling [9][10] and (ii) oversampling [11]. The main advantage of these techniques is the digitalization of the observed jitter that guarantees the robustness of the design.…”

Section: ) Jitter Estimatormentioning

confidence: 99%

Auto-adaptive ultra-low power IC

Bosio

Debaud

Girard

et al. 2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

Self Cite

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High frequency jitter estimator for SoCs

Gall

Alhakim

Valka

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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This paper presents an Embedded Test Instrument (ETI) for the estimation of the High Frequency (HF) jitter of an observed clock signal. The ETI uses a second reference clock for under-sampling the observed signal similar to previous approaches. However, the analysis of the test response does not require the construction of the Cumulative Distributed Function (CDF) of the jitter as in previous approaches. Instead, the HF jitter of the input observed signal is transformed at the output of the ETI into a digital value that corresponds to a number of unwanted signal transitions. We demonstrate in this paper that the transfer function of the ETI defined by the ratio of the number of unwanted signal transitions and the input HF jitter is linear. This property leads to a simple circuit implementation. The linearity of the ETI is demonstrated firstly by behavioral simulation, using a theoretical model of the output of the undersampling process, and secondly by transistor-level simulation using the 65 nm CMOS bulk technology by ST Microelectronics.We also present experimental measurements that have been carried out using an FPGA-based test platform to validate the linearity of the transfer function in the presence of non-idealities that can affect the ETI. Finally, we demonstrate the exploitation of the ETI within Systems-on-Chip (SoCs) produced in highvolume by ST Microelectronics.

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iBoX — Jitter based Power Supply Noise sensor

Cited by 2 publications

References 4 publications

Auto-adaptive ultra-low power IC

Auto-adaptive ultra-low power IC

High frequency jitter estimator for SoCs

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