Impact of Downscaling on High-Frequency Noise Performance of Bulk and SOI MOSFETs

Pailloncy, G.; Raynaud, C.; Vanmackelberg, M.; Danneville, F.; Lepilliet, S.; Raskin, Jean‐Pierre; Dambrine, G.

doi:10.1109/ted.2004.834902

Cited by 31 publications

(16 citation statements)

References 13 publications

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“…As shown in Figure 6, the gain of LNA circuit with W f = 0 5 m is larger than that of W f = 17 5 m. For the same total width, the number of finger of the transistor is increasing with the decreasing of the unity width, the gate resistance will decrease and cause f MAX defined in Refs. [1,9] to increase. While the finger number increases, the overlap capacitance of the transistor will increase which results in f T decreasing.…”

Section: Simulation Resultsmentioning

confidence: 94%

Design and Optimization of a Milli-Meter Wave Amplifier Using Nano-Scale CMOS Devices

Xu¹,

Yu²,

Lim³

et al. 2014

Nanosci Nanotechnol Lett

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This letter reviews some fundamental trade-offs in RF amplifier design as well as optimization from devices to circuit design using nano-scale CMOS process, that reduces the impact of manufacturing variations on integrated wideband low noise amplifiers (LNA). The design considerations include the unity-gain frequency, high frequency noise, power consumption and linearity of active devices in addition to accurate physic models for passive components such as RF and transmission lines. All these considerations are traded off among a system designs aspect. For an example in a commercial 65 nm CMOS technology design, by optimizing the unity width of the transistors and the transmission lines, a three-stage LNA achieves a peak gain of 22.3 dB at 60 GHz with a Noise Figure of 5.17 dB. Each stage consumes 5.2 mA from a supply voltage of 1.5 V. By using Monte Carlo simulation, the LNA with optimized transistor and interconnects has a higher gain and lower Noise Figure. The circuit is able to work robustly against process variations by optimizing the transistors and the transmission lines.

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Section: Simulation Resultsmentioning

confidence: 94%

Design and Optimization of a Milli-Meter Wave Amplifier Using Nano-Scale CMOS Devices

Xu¹,

Yu²,

Lim³

et al. 2014

Nanosci Nanotechnol Lett

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show abstract

“…Y-parameters are computed using the 2-D device simulator with an ac small signal device simulation is performed over a frequency range, and the Y-parameters are computed. RF-FOMs parameters can be calculated from the small signal equivalent circuit extracted from the Y-parameters computed using the active transmission line analysis identifying each branch of Pi equivalent circuit [40]. f T is extracted when current gain drops to unity (9Y 21 /Y 11 9 ¼1), and f max is extracted when Mason's unilateral gain drops to unity.…”

Section: Rf Performance Analysismentioning

confidence: 99%

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

Sarkar

Das

De³

et al. 2012

Microelectronics Journal

166

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“…RF-FOMs parameters can be calculated from the small signal equivalent circuit extracted from the Y parameters computed using the active transmission line analysis identifying each branch of Pi equivalent circuit [39]. Then an advanced two port network RF extraction post processing tool is used to generate the different RF-FOMs (f T and f max ) by converting admittances and capacitances to H -parameters as [40] f…”

Section: Rf Performance Investigationsmentioning

confidence: 99%

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

Sarkar

De²,

Dey

et al. 2012

J Comput Electron

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We report a systematic, quantitative investigation of analog and RF performance of cylindrical surroundinggate (SRG) silicon MOSFET. To derive the model, a pseudotwo-dimensional (2-D) approach applying Gauss's law in the channel region is extended for the cylindrical SRG MOSFET. Based on surface potential approach, expressions of drain current and differential capacitances are obtained analytically. Analog/RF figures of merit of SRG MOSFET are studied, including transconductance efficiency g m /I d , intrinsic gain, output resistance, cutoff frequency f T , maximum oscillation frequency f max and gain bandwidth product GBW. The trends related to their variations along the downscaling of dimension are provided. In order to validate our model, the modeled predictions have been extensively compared with the simulated characteristics obtained from the ATLAS device simulator and a nice agreement is observed with a wide range of geometrical parameters.

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Impact of Downscaling on High-Frequency Noise Performance of Bulk and SOI MOSFETs

Cited by 31 publications

References 13 publications

Design and Optimization of a Milli-Meter Wave Amplifier Using Nano-Scale CMOS Devices

Design and Optimization of a Milli-Meter Wave Amplifier Using Nano-Scale CMOS Devices

Effect of gate engineering in double-gate MOSFETs for analog/RF applications

Analog and RF performance investigation of cylindrical surrounding-gate MOSFET with an analytical pseudo-2D model

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