2021
DOI: 10.1088/1361-6641/abdba3
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Impact of heavy ion particle strike induced single event transients on conventional and π – Gate AlGaN/GaN HEMTs

Abstract: This paper presents an extensive Victory TCAD based assessment to evaluate the device performance under heavy ion particle strike induced single event effects (SEEs). The impact of SEEs on π-shaped AlGaN/GaN HEMT architecture has been compared with conventional AlGaN/GaN HEMT. For validation of simulation, models have been calibrated against the experimental data of in-house fabricated GaN HEMTs on SiC wafers, after which π-shaped architecture is realized using Silvaco's Victory Process simulation tools. Compa… Show more

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Cited by 12 publications
(7 citation statements)
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“…The capture cross sections for electrons (σ n ) and holes �σ p � were set to 1 × 10 −13 cm 2 . Further, since the bulk traps in GaN buffer are responsible for the degradation in the output admittance parameters [42][43][44], acceptor type traps with E T = 0.45 eV and bulk trap density of 1.5 × 10 16 cm −3 were defined in GaN buffer with capture cross sections, σ n and σ p set to 1 × 10 −13 cm 2 respectively. The trapping definitions are in accordance with the experimental studies on similar AlGaN/GaN heterostructures [42][43][44].…”
Section: B Simulation and Calibration Methodologymentioning
confidence: 99%
See 1 more Smart Citation
“…The capture cross sections for electrons (σ n ) and holes �σ p � were set to 1 × 10 −13 cm 2 . Further, since the bulk traps in GaN buffer are responsible for the degradation in the output admittance parameters [42][43][44], acceptor type traps with E T = 0.45 eV and bulk trap density of 1.5 × 10 16 cm −3 were defined in GaN buffer with capture cross sections, σ n and σ p set to 1 × 10 −13 cm 2 respectively. The trapping definitions are in accordance with the experimental studies on similar AlGaN/GaN heterostructures [42][43][44].…”
Section: B Simulation and Calibration Methodologymentioning
confidence: 99%
“…Further, since the bulk traps in GaN buffer are responsible for the degradation in the output admittance parameters [42][43][44], acceptor type traps with E T = 0.45 eV and bulk trap density of 1.5 × 10 16 cm −3 were defined in GaN buffer with capture cross sections, σ n and σ p set to 1 × 10 −13 cm 2 respectively. The trapping definitions are in accordance with the experimental studies on similar AlGaN/GaN heterostructures [42][43][44]. Yang et al [45] have also demonstrated through DLTS measurements the evolution of electron and hole traps in doped GaN cap layers, which realize enhancement mode operation.…”
Section: B Simulation and Calibration Methodologymentioning
confidence: 99%
“…Compared with Si and GaAs, the breakdown eld of the third-generation semiconductor materials such as GaN and SiC is one order of magnitude higher [8]. In the same size, the breakdown voltage of GaN and SiC devices is one order of magnitude higher than that of Si and GaAs devices, ensuring the high-power output of the device [9][10][11][12]. Because SiC lacks a heterojunction structure, the device structure mainly uses metal semiconductor eld effect transistors, and eld effect transistors are surface devices, the carrier transport is affected by the surface, resulting in low mobility, which limits the devices in the high-frequency eld applications.…”
Section: Introductionmentioning
confidence: 99%
“…As the size of the MOSFET decreases, several short-channel phenomena such as hot carriers, DIBL (drain induced barrier lowering), 1 leakage current, and interface trap charges 2 reduce the device's performance. Numerous improved topologies, such as multigate MOSFETs, 3 pi-gate MOSFETs, 4 and cylindrical MOSFETs, 5 have been described to address these deficiencies. High-k dielectrics with metal gate-stacks, shallow junctions, and replacing the silicon channel with materials that can move more electrons are some of the techniques that can make it easier to make more advanced and aggressive scaling of MOSFETs.…”
mentioning
confidence: 99%