Impact of temperature on negative capacitance based Junctionless Accumulation Mode Ferroelectric FET(JAM-FE-FET)

Yadav, Snehlata; Rewari, Sonam; Pandey, Rajeshwari

doi:10.1109/icecet55527.2022.9872837

Cited by 2 publications

(1 citation statement)

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“…In particular, the urgent problem to be addressed is the increase in power dissipation resulting from the decrease in transistor size. To solve this problem, active research is being conducted on negative capacitance fieldeffect transistor (NCFET) using a ferroelectric, which can reduce the parasitic current in the subthreshold region [1][2][3].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric

Hakkee Jung

2024

Int. j. eng. technol. innov.

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This study presents an analytical model for the drain-induced barrier lowering (DIBL) of a junctionless gate-all-around FET with ferroelectric, utilizing a 2D potential model. A multilayer structure of metal-ferroelectric-metal-insulator-semiconductor is used as the gate, as well as the remanent polarization and coercive field values corresponding to HZO are used. The DIBLs obtained with the proposed model demonstrate good agreement with those obtained using the second derivative method, which relies on the 2D relationship between drain current and gate voltage. The results demonstrate that an increase in ferroelectric thickness leads to a negative DIBL value due to the ferroelectric charge. Additionally, there exists an inverse relationship between ferroelectric thickness and channel length to achieve a DIBL value of 0. This condition is satisfied only with the increase of the ferroelectric thickness as the channel radius and insulator thickness increase. The DIBLs increase with higher remanent polarization and lower coercive field, remaining constant when the ratio of remanent polarization and coercive field is maintained.

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Section: Introductionmentioning

confidence: 99%