Impact of the Sub-Resting Membrane Potential on Accurate Inference in Spiking Neural Networks

Hwang, Sungmin; Chang, Jeesoo; Oh, Misook; Lee, Jong-Ho; Park, Byung‐Gook

doi:10.1038/s41598-020-60572-8

Cited by 21 publications

(19 citation statements)

References 26 publications

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“…For high performance in HNNs, various synaptic arrays and neuron circuits suitable for efficient architectures and learning algorithms have been researched [4][5][6][7][8]. Specifically, both excitatory (G + ) and inhibitory (G -) synaptic arrays are important to improve the accuracy of HNNs [9][10][11]. Neuron circuits that use large capacitors (≥ 0.1 pF) and many transistors (≥ 11 MOSFETs) to process simultaneously signals from these two types of synapses have been reported [11][12][13], resulting in increased power consumption and a larger area.…”

Section: Introductionmentioning

confidence: 99%

“…Specifically, both excitatory (G + ) and inhibitory (G -) synaptic arrays are important to improve the accuracy of HNNs [9][10][11]. Neuron circuits that use large capacitors (≥ 0.1 pF) and many transistors (≥ 11 MOSFETs) to process simultaneously signals from these two types of synapses have been reported [11][12][13], resulting in increased power consumption and a larger area. Note that processing these signals simultaneously can reduce memory usage and simplify the peripheral circuitry.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

et al. 2020

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A positive-feedback (PF) neuron device capable of threshold tuning and simultaneously processing excitatory (G +) and inhibitory (G-) signals is experimentally demonstrated to replace conventional neuron circuits, for the first time. Thanks to the PF operation, the PF neuron device with steep switching characteristics can implement integrate-and-fire (IF) function of neurons with low-energy consumption. The structure of the PF neuron device efficiently merges a gated PNPN diode and a single MOSFET. Integrateand-fire (IF) operation with steep subthreshold swing (SS < 1 mV/dec) is experimentally implemented by carriers accumulated in an n floating body of the PF neuron device. The carriers accumulated in the n floating body are discharged by an inhibitory signal applied to the merged FET. Moreover, the threshold voltage (Vth) of the proposed PF neuron is controlled by using a charge storage layer. The low-energy consuming PF neuron circuit (~ 0.62 pJ/spike) consists of one PF device and only five MOSFETs for the IF and reset operation. In a high-level system simulation, a deep-spiking neural network (D-SNN) based on PF neurons with four hidden layers (1024 neurons in each layer) shows high-accuracy (98.55%) during a MNIST classification task. The PF neuron device provides a viable solution for high-density and low-energy neuromorphic systems.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

et al. 2020

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“…Current-mirror-based neurons [8], [9] and op-amp-based neurons [10], [11] are the two types of analog I&F neurons commonly used in hardware-based SNNs. The I&F neurons receive pre-synaptic spikes from the preceding layer and accumulate them as membrane potential in the voltage domain.…”

Section: Time-domain Neuron a Limitations Of Voltage-domain Neuronsmentioning

confidence: 99%

“…Note that when an input spike is modulated with a positive (negative) weight, the ICO frequency should increase (decrease). A straightforward way to implement this is to use a current mirror as [9], where PMOS/NMOS are used to add/subtract current flowing into the ICO, respectively. However, this implementation suffers from a mismatch between PMOS and NMOS, which manifests itself as weight error and leads to inference accuracy degradation.…”

Section: Low-power Design Of Time-domain Neuronmentioning

confidence: 99%

Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons

Joonghyun¹,

Shin²,

Kim³

et al. 2022

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Due to the limitations of realizing artificial neural networks on prevalent von Neumann architectures, recent studies have presented neuromorphic systems based on spiking neural networks (SNNs) to reduce power and computational cost. However, conventional analog voltage-domain integrate-and-fire (I&F) neuron circuits, based on either current mirrors or op-amps, pose serious issues such as nonlinearity or high power consumption, thereby degrading either inference accuracy or energy efficiency of the SNN. To achieve excellent energy efficiency and high accuracy simultaneously, this paper presents a low-power highly linear time-domain I&F neuron circuit. Designed and simulated in a 28 nm CMOS process, the proposed neuron leads to more than 4.3 × lower error rate on the MNIST inference over the conventional current-mirror-based neurons. In addition, the power consumed by the proposed neuron circuit is simulated to be 0.230 µW per neuron, which is orders of magnitude lower than the existing voltage-domain neurons.

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“…However, conventional I & F neuron circuits are vulnerable to off-currents continuously occurring in the synaptic array because the integration part passes the input synaptic current to the membrane capacitor without any control. To analyze the effect of the synaptic off-current on the neuron circuit, we can model the analog relationship between the current and based on previous work [34]. The of the conventional I & F neuron circuit at time t can be expressed as:…”

Section: A Conventional I and F Neuron Circuitmentioning

confidence: 99%

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

et al. 2021

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In this study, we propose an analog CMOS integrate-and-fire (I & F) neuron circuit with a synaptic off-state current blocking operation. The proposed circuit prevents unintended potential changes in the membrane capacitor owing to the off-state current of synaptic devices, thereby preventing a decrease in the accuracy of the spiking neural network (SNN) inference system. Compared to the conventional I & F neuron circuit, the basic I & F and synaptic off-current blocking operations of the proposed I & F neuron circuit were confirmed in a circuit-level simulation. Furthermore, to verify the effect of the proposed circuit on the neural network, a multi-layer SNN simulation was performed, and the accuracy of the inference system was compared for the conventional and proposed I & F neuron circuits. The simulation and analysis results demonstrate the robustness of the I & F neuron circuit to the drop in accuracy of inference systems due to off-state currents in synaptic devices. INDEX TERMS neuromorphic system, CMOS-based integrate-and-fire (I & F) neuron circuit, spiking neural networks (SNNs), synaptic off-state current blocking operation, TCAD simulation, SPICE simulation, SNN high-level simulation.

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Impact of the Sub-Resting Membrane Potential on Accurate Inference in Spiking Neural Networks

Cited by 21 publications

References 26 publications

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems

Energy-Efficient High-Accuracy Spiking Neural Network Inference Using Time-Domain Neurons

Integrate-and-Fire Neuron Circuit With Synaptic Off-Current Blocking Operation

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