Impact of two gate oxide with no junction metal oxide semiconductor field effect transistor- an analytical model

Darwin, S.; Samuel, T. S. Arun; Vimala, P.

doi:10.1016/j.physe.2019.113803

Cited by 12 publications

(3 citation statements)

References 20 publications

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“…When combined with HD oxide, the capacitive impact is reduced further due to the lower dielectric constant of SiO 2. 22 …”

Section: Resultsmentioning

confidence: 99%

“…Recently, inverted L‐shaped pockets, 19 GHD TFET incorporating a source channel epi‐layer line pocket, 17 and fully extended source to drain epi‐layer pocket have also been reported 21 . At such scaled nano‐dimensions, especially for heterojunction designs, studies on the design reliability aspects become essential; 2,6,16,17,22,23 however, not much work has been that in that respect. Further, designs particularly based on SiGe/Si line tunneling heterojunctions 7‐14 that have been actually demonstrated till now adhere to fabricated Si pockets lying in the range of 6‐7 nm, 7,10 with the very recent gate‐normal TFET comprising a relaxed ~10 nm line pocket 9 .…”

Section: Introductionmentioning

confidence: 99%

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Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Ashita

Loan

Alkhammash

et al. 2021

Int J Numerical Modelling

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In this work, we propose and investigate a new pocket‐based Si0.55Ge0.45/Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with and without a heterogeneous dielectric (HD) gate oxide. Miller capacitance is significantly reduced with the GSLP design, which is further improved by the HD gate oxide leading to full overshoot/undershoot suppression capability in transient response. Further, a steep switching with more than one order improvement in ON current is achieved when compared to state‐of‐the‐art line pocket designs. As a result, an ~98.8% and ~88% improved intrinsic delay (CGGVDD/ION) is achieved in comparison to dual line pocket and non‐pocketed designs, respectively. Additionally, an improved worst‐case trap‐charge tolerance, reduced pocket‐width‐induced fluctuations, and excellent immunity to gate misalignment‐induced fluctuations are achievable just by replacing the gate‐aligned parallel‐line pockets with a vertically aligned single‐lateral pocket (LP) improving the design reliability. A Ge/Si HD‐GSLP TFET design further offers stable ON currents with SS < 60 mV/dec over a feasible range of pocket widths between ~6 and 8 nm at VDS = VGS = 0.7 V.

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“…When combined with HD oxide, the capacitive impact is reduced further due to the lower dielectric constant of SiO 2. 22 …”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Ashita

Loan

Alkhammash

et al. 2021

Int J Numerical Modelling

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“…In particular, various structures like junctionless (JL) MOSFETs, FinFETs, and GAA (Gate-All-Around) FETs have been actually used in the integrated circuits, which is ultimately a structure for improving the controllability of the channel charge by the gate voltage [7][8][9][10]. Among these structures, the structure with the greatest potential is the GAA FET structure.…”

Section: Introductionmentioning

confidence: 99%

Impact of Gate Metal Work-function for On-to-off Current Ratio and Threshold Voltage in Junctionless Gate-All-Around (GAA) MOSFET Stacked with SiO2 and High-k Dielectric

Jung¹

2023

IJETAE

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The relationship among the on-to-off current ratio, threshold voltage, and the gate metal work-function is investigated for a junctionless (JL) Gate-All-Around (GAA) MOSFET with a gate oxide film in which SiO2 and a high-k dielectric material are stacked. The JL structure works in the accumulation state, and the threshold voltage is defined as the gate voltage when the minimum potential in the channel becomes Fermi potential. The on-to-off current ratio Ion/Ioff is obtained by obtaining on-current Ion at the threshold voltage and off-current Ioff at the gate voltage of 0 V. As a result, if the channel doping concentration and silicon radius are increased to reduce the channel resistance, the on-to-off current ratio decreases along with the threshold voltage, but this problem can be solved through the increasing of the gate metal workfunction. In addition, even when the relative permittivity of the high-k dielectric is increased from 3.9 to 20, the gate metal work-function to maintain any on-to-off current ratio and threshold voltage is very slightly changed. Therefore it will be possible to improve the controllability of the gate by increasing the permittivity of the high-k dielectric without change in the work-function. The reduction of the channel resistance of the JL GAA MOSFET is possible with the stacked gate oxide while maintaining a reasonable on-to-off current ratio and threshold voltage by adjusting the gate metal work-function

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