GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference 2009
DOI: 10.1109/glocom.2009.5426313
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Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals

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Cited by 12 publications
(11 citation statements)
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References 9 publications
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“…The stand-alone and the integrated de-/ciphering unit in the sDMA controller use both an equal timing configuration of 4 ns per byte for encryption and decryption. This is the maximum performance value derived from hardware implementations presented in [21]. Additionally, the header decoding units in the sDMA controller work with a timing of one cycle per byte.…”
Section: Resultsmentioning
confidence: 99%
“…The stand-alone and the integrated de-/ciphering unit in the sDMA controller use both an equal timing configuration of 4 ns per byte for encryption and decryption. This is the maximum performance value derived from hardware implementations presented in [21]. Additionally, the header decoding units in the sDMA controller work with a timing of one cycle per byte.…”
Section: Resultsmentioning
confidence: 99%
“…They focused on optimizing tables and adders in the critical path of the design, and provided a comparison with other implementations and other ciphers. Hessel et al [13] analyzed various aspects of SNOW 3G and AES; both are used in LTE. They determined how the system changes with respect to data rate.…”
Section: Related Workmentioning
confidence: 99%
“…From Table 1, we find the implementations in [9,10,11] are potential candidates for using in 5G since they meet the required throughput of 5G and Table 1. AES Implementations present their energy requirements which enable us to make a meaningful analysis.…”
Section: Aesmentioning
confidence: 99%
“…This implementation appears to be a very good candidate for a 5G phone. In [11], the implementation achieves the required throughput without any need of scaling up but it spends almost 30 times more energy than that of [9].…”
Section: Aesmentioning
confidence: 99%