Implementation and comparison of VLSI architectures of 16 bit carry select adder using Brent Kung adder

Kumar, N. Udaya; Sindhuri, K. Bala; Teja, K. Durga; Satish, D. Sai

doi:10.1109/ipact.2017.8244982

Cited by 16 publications

(4 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Delay and area are the two prime factors considered when designing most digital systems. These systems heavily rely on adders, multipliers, and squarers [21][22][23]. The current multipliers and squarers (precisely their related adders), which form the central part of these systems, affect their speed and area [18].…”

Section: Methodsmentioning

confidence: 99%

“…To refine the performance of the proposed 6-bit squarer in terms of area and delay, this work offers the use of a 6-bit improved Brent-Kung adder IBK-CSLA [9,22] with a 4-bit binary to access-1 convertor (4bit BEC) to perform the addition of 2nd stage as demonstrated in Figure . 6. The BEC employs less area and generates less delay than the RCA or any other adder.…”

Section: Dedicated 3-bit Squarermentioning

confidence: 99%

See 1 more Smart Citation

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

View full text Add to dashboard Cite

Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of 32-bit floating-point numbers. The paper also offers three architectures for 24-bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12-bit, and 24-bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24-bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with (3*3) VM introduces the lowest area and delay.

show abstract

Section: Methodsmentioning

confidence: 99%

Section: Dedicated 3-bit Squarermentioning

confidence: 99%

Vedic-Based Squarers with High Performance

Al-Assfor

AL-Furati

Rashed

2021

IJEEI

View full text Add to dashboard Cite

show abstract

“…Parallel prefix adders are fast adder circuits that can be used for PA binary addition. Parallel prefix adders, such as Sklansky [8], KS [9][10][11][12], Brent-Kung (BK) [13], Beaumont-smith (BS) [14] as well the carry look-ahead (CLA) [15] and ripple carry adder (RCA) [16] are applied in the conventional 12-bit pipelined PA design, as shown in Figure 3. The PAs'…”

Section: Frequency Control Word ( Fcw )mentioning

confidence: 99%

An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

Alkurwy

Ali

Islam

et al. 2021

IJECE

View full text Add to dashboard Cite

This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the kogge-stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

show abstract

“…A number of adders have been designed based on the prefix concept and used for binary addition in the phase accumulator designs. An example of these adders, as KS [16], Sklanski (SK) [17], Brent-Kunt (BK) [18], and Beaumont-Smith (BS) adder [19].…”

Section: Phase Accumulator Design Based On Fast Addersmentioning

confidence: 99%

Review of high-speed phase accumulator for direct digital frequency synthesizer

Abbas¹

2020

IJECE

View full text Add to dashboard Cite

A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

show abstract

Implementation and comparison of VLSI architectures of 16 bit carry select adder using Brent Kung adder

Cited by 16 publications

References 7 publications

Vedic-Based Squarers with High Performance

Vedic-Based Squarers with High Performance

An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

Review of high-speed phase accumulator for direct digital frequency synthesizer

Contact Info

Product

Resources

About