Implementation and optimization of multifrontal method for FT-M6678

Abstract

The numerical solution of large sparse linear systems is a fundamental aspect of many large-scale scientific and engineering computations. The multifrontal method, as a prevalent direct solving approach, currently lacks a corresponding implementation on domestic Digital Signal Processor platforms. With the development of the domestic FT series highperformance digital signal processors, there is an urgent need to meet the demand for efficient numerical solutions of large sparse linear systems in practical engineering applications. In response to the above-mentioned issue, We implement and optimize the multifrontal method for the FT-M6678 platform. By analyzing the hardware architecture of the FT-M6678 and the characteristics of the multifrontal method algorithm, we employ compilation optimization, loop unrolling, and single-instruction multiple data vectorization techniques. This fully leverages the independent functional units and register resources of the platform, achieving instruction-level and data-level parallelism. Considering the storage hierarchy of the FT-M6678, we configure the first and second-level caches, set attributes for the cacheability of external memory, and design memory layout based on memory bandwidth. We allocate different data and code segments to distinct storage areas, optimizing the storage and access of data. Experimental test data is sourced from the University of Florida Sparse Matrix Collection. The acceleration ratio of the algorithm after optimization on the FT-M6678 platform ranges from 16.0~38.9. Compared to the TMS320C6678 platform, the performance improvement can reach up to 2.3 times.