Implementation of memory tester consisting of SRAM-based reconfigurable cells

Abstract

A scheme for testing SRAMs is proposed with a tester circuit consisting of SRAM-based reconfigurable cells. We first show an approach to reduce the number of reconfigurable cells required for the tester circuit. We then propose a tester for a 4-Mbit SRAM with reconfigurable cells of 16-bit data SRAMs. We also report the implementation of the proposed circuit. Four 16-bit reconfigurable cells, each of which consists of an SRAM and two CPLDs, were implemented, and mounted on a board. We confirmed that the tester functions correctly by performing a marching test. keywords: SRAM test, SRAM-based reconfigurable cell, memory tester, marching test