Implementation of power efficient 8-bit reversible linear feedback shift register for BIST

Kumar, Y. G. Praveen; Kariyappa, B S; Kurian, M Z

doi:10.1109/icisc.2017.8068620

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Implementation of power efficient 8-bit reversible linear feedback shift register for BIST

Cited by 7 publications

References 5 publications

Power Efficient Multistage Linear Feedback Shift Register Counters Design in 130-nm CMOS for Large-Scale Applications

Power Efficient Multistage Linear Feedback Shift Register Counters Design in 130-nm CMOS for Large-Scale Applications

A 500-MHz 32-bit DETFF-based Shift Register Utilizing 40-nm CMOS Technology

Design and Verification of Power Efficient Built-In Self-Test

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