Implementation of power gating circuit for standby leakage power reduction

Abstract

This paper presents a technique which is called Asynchronous Adiabatic Power gated Logic (AAPL) which combines the benefit of both asynchronous and adiabatic logic. Each pipeline stage in the AAPL consists of adiabatic logic gate and handshake controller. Adiabatic logic gate is used to perform the logic function of the stage and the handshake controller is used to communicate with the neighboring devices and provide power to logic gates. In the AAPL circuit, logic gates obtain power and turn into active only when performing useful computations, and idle logic gates are not powered and thus have negligible leakage power dissipation. The Partial Charge Reuse (PCR) mechanism can also be integrated in this paper which is used to control the charge reuse between two stages.